Commit a6e9d7ef authored by Sai Prakash Ranjan's avatar Sai Prakash Ranjan Committed by Bjorn Andersson
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soc: qcom: llcc: Add configuration data for SM8450 SoC 



Add LLCC configuration data for SM8450 SoC.

Signed-off-by: default avatarSai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/fec944cb8f2a4a70785903c6bfec629c6f31b6a4.1643355594.git.quic_saipraka@quicinc.com
parent 424ad93c

drivers/soc/qcom/llcc-qcom.c

+34 −0
Original line number Diff line number Diff line
@@ -226,6 +226,32 @@ static const struct llcc_slice_config sm8350_data[] = { 
	{ LLCC_CPUHWT,   5, 512,   1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 },

};



static const struct llcc_slice_config sm8450_data[] =  {

	{LLCC_CPUSS,     1, 3072, 1, 0, 0xFFFF, 0x0,   0, 0, 0, 1, 1, 0, 0 },

	{LLCC_VIDSC0,    2,  512, 3, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_AUDIO,     6, 1024, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0 },

	{LLCC_MDMHPGRW,  7, 1024, 3, 0, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_MODHW,     9, 1024, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_CMPT,     10, 4096, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_GPUHTW,   11,  512, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_GPU,      12, 2048, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 1, 0 },

	{LLCC_MMUHWT,   13,  768, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0 },

	{LLCC_DISP,     16, 4096, 2, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_MDMPNG,   21, 1024, 1, 1, 0xF000, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_AUDHW,    22, 1024, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0 },

	{LLCC_CVP,      28,  256, 3, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_MODPE,    29,   64, 1, 1, 0xF000, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_APTCM,    30, 1024, 3, 1, 0x0,    0xF0,  1, 0, 0, 1, 0, 0, 0 },

	{LLCC_WRCACHE,  31,  512, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 1, 0, 0 },

	{LLCC_CVPFW,    17,  512, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_CPUSS1,    3, 1024, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_CAMEXP0,   4,  256, 3, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_CPUMTE,   23,  256, 1, 1, 0x0FFF, 0x0,   0, 0, 0, 0, 1, 0, 0 },

	{LLCC_CPUHWT,    5,  512, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 1, 0, 0 },

	{LLCC_CAMEXP1,  27,  256, 3, 1, 0xFFFF, 0x0,   0, 0, 0, 1, 0, 0, 0 },

	{LLCC_AENPU,     8, 2048, 1, 1, 0xFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0 },

};



static const u32 llcc_v1_2_reg_offset[] = {

	[LLCC_COMMON_HW_INFO]	= 0x00030000,

	[LLCC_COMMON_STATUS0]	= 0x0003000c,
@@ -285,6 +311,13 @@ static const struct qcom_llcc_config sm8350_cfg = { 
	.reg_offset	= llcc_v1_2_reg_offset,

};



static const struct qcom_llcc_config sm8450_cfg = {

	.sct_data       = sm8450_data,

	.size           = ARRAY_SIZE(sm8450_data),

	.need_llcc_cfg	= true,

	.reg_offset	= llcc_v21_reg_offset,

};



static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;



/**
@@ -713,6 +746,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { 
	{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },

	{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },

	{ .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg },

	{ .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg },

	{ }

};

include/linux/soc/qcom/llcc-qcom.h

+5 −0
Original line number Diff line number Diff line
@@ -35,7 +35,12 @@ 
#define LLCC_WRCACHE     31

#define LLCC_CVPFW       32

#define LLCC_CPUSS1      33

#define LLCC_CAMEXP0     34

#define LLCC_CPUMTE      35

#define LLCC_CPUHWT      36

#define LLCC_MDMCLAD2    37

#define LLCC_CAMEXP1     38

#define LLCC_AENPU       45



/**

 * struct llcc_slice_desc - Cache slice descriptor