Commit a6e917b7 authored by Jacky Bai's avatar Jacky Bai Committed by Shawn Guo
Browse files

arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board 



Add the basic dts file for i.MX8ULP EVK board.
Only the necessary devices for minimal system boot up are enabled:
enet, emmc, usb, console uart.

some of the devices' pin status may lost during low power mode,
so additional sleep pinctrl properties are included by default.

Reviewed-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent fe6291e9

arch/arm64/boot/dts/freescale/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb 
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb



dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb

dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb

arch/arm64/boot/dts/freescale/imx8ulp-evk.dts

0 → 100644
+64 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright 2021 NXP

 */



/dts-v1/;



#include "imx8ulp.dtsi"



/ {

	model = "NXP i.MX8ULP EVK";

	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";



	chosen {

		stdout-path = &lpuart5;

	};



	memory@80000000 {

		device_type = "memory";

		reg = <0x0 0x80000000 0 0x80000000>;

	};

};



&lpuart5 {

	/* console */

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&pinctrl_lpuart5>;

	pinctrl-1 = <&pinctrl_lpuart5>;

	status = "okay";

};



&usdhc0 {

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&pinctrl_usdhc0>;

	pinctrl-1 = <&pinctrl_usdhc0>;

	non-removable;

	bus-width = <8>;

	status = "okay";

};



&iomuxc1 {

	pinctrl_lpuart5: lpuart5grp {

		fsl,pins = <

			MX8ULP_PAD_PTF14__LPUART5_TX	0x3

			MX8ULP_PAD_PTF15__LPUART5_RX	0x3

		>;

	};



	pinctrl_usdhc0: usdhc0grp {

		fsl,pins = <

			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43

			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042

			MX8ULP_PAD_PTD10__SDHC0_D0	0x43

			MX8ULP_PAD_PTD9__SDHC0_D1	0x43

			MX8ULP_PAD_PTD8__SDHC0_D2	0x43

			MX8ULP_PAD_PTD7__SDHC0_D3	0x43

			MX8ULP_PAD_PTD6__SDHC0_D4	0x43

			MX8ULP_PAD_PTD5__SDHC0_D5	0x43

			MX8ULP_PAD_PTD4__SDHC0_D6	0x43

			MX8ULP_PAD_PTD3__SDHC0_D7	0x43

			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042

		>;

	};

};