Commit a6de636e authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/soc21: don't expose AV1 if VCN0 is harvested 



Only VCN0 supports AV1.

Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3c6f90f4

drivers/gpu/drm/amd/amdgpu/soc21.c

+48 −13
Original line number Diff line number Diff line
@@ -48,19 +48,31 @@ 
static const struct amd_ip_funcs soc21_common_ip_funcs;



/* SOC21 */

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array[] =

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] =

{

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},

};



static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode =

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] =

{

	.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array),

	.codec_array = vcn_4_0_0_video_codecs_encode_array,

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},

};



static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array[] =

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 =

{

	.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),

	.codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,

};



static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 =

{

	.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),

	.codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,

};



static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] =

{

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
@@ -69,23 +81,46 @@ static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array[ 
	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},

};



static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode =

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] =

{

	.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array),

	.codec_array = vcn_4_0_0_video_codecs_decode_array,

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},

};



static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 =

{

	.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),

	.codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,

};



static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 =

{

	.codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),

	.codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,

};



static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,

				 const struct amdgpu_video_codecs **codecs)

{

	switch (adev->ip_versions[UVD_HWIP][0]) {

	if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))

		return -EINVAL;



	switch (adev->ip_versions[UVD_HWIP][0]) {

	case IP_VERSION(4, 0, 0):

	case IP_VERSION(4, 0, 2):

		if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {

			if (encode)

				*codecs = &vcn_4_0_0_video_codecs_encode_vcn1;

			else

				*codecs = &vcn_4_0_0_video_codecs_decode_vcn1;

		} else {

			if (encode)

			*codecs = &vcn_4_0_0_video_codecs_encode;

				*codecs = &vcn_4_0_0_video_codecs_encode_vcn0;

			else

			*codecs = &vcn_4_0_0_video_codecs_decode;

				*codecs = &vcn_4_0_0_video_codecs_decode_vcn0;

		}

		return 0;

	default:

		return -EINVAL;