Commit a6c8056d authored by Tero Kristo's avatar Tero Kristo Committed by Tony Lindgren
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ARM: dts: omap5: convert IOMMUs to use ti-sysc 



Convert omap5 IOMMUs to use ti-sysc instead of legacy omap-hwmod based
implementation. Enable the IOMMUs also while doing this.

Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 22f8d664

arch/arm/boot/dts/omap5-l4.dtsi

+8 −3
Original line number Diff line number Diff line
@@ -349,7 +349,6 @@ 


		target-module@66000 {			/* 0x4a066000, ap 23 0a.0 */

			compatible = "ti,sysc-omap2", "ti,sysc";

			ti,hwmods = "mmu_dsp";

			reg = <0x66000 0x4>,

			      <0x66010 0x4>,

			      <0x66014 0x4>;
@@ -364,12 +363,18 @@ 
			/* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */

			clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;

			clock-names = "fck";

			resets = <&prm_dsp 1>;

			reset-names = "rstctrl";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x66000 0x1000>;



			/* mmu_dsp cannot be moved before reset driver */

			status = "disabled";

			mmu_dsp: mmu@0 {

				compatible = "ti,omap4-iommu";

				reg = <0x0 0x100>;

				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;

				#iommu-cells = <0>;

			};

		};



		target-module@70000 {			/* 0x4a070000, ap 79 2e.0 */

arch/arm/boot/dts/omap5.dtsi

+26 −14
Original line number Diff line number Diff line
@@ -186,22 +186,34 @@ 
			#gpio-cells = <2>;

		};



		mmu_dsp: mmu@4a066000 {

			compatible = "ti,omap4-iommu";

			reg = <0x4a066000 0x100>;

			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "mmu_dsp";

			#iommu-cells = <0>;

		};

		target-module@55082000 {

			compatible = "ti,sysc-omap2", "ti,sysc";

			reg = <0x55082000 0x4>,

			      <0x55082010 0x4>,

			      <0x55082014 0x4>;

			reg-names = "rev", "sysc", "syss";

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |

					 SYSC_OMAP2_SOFTRESET |

					 SYSC_OMAP2_AUTOIDLE)>;

			clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;

			clock-names = "fck";

			resets = <&prm_core 2>;

			reset-names = "rstctrl";

			ranges = <0x0 0x55082000 0x100>;

			#size-cells = <1>;

			#address-cells = <1>;



		mmu_ipu: mmu@55082000 {

			mmu_ipu: mmu@0 {

				compatible = "ti,omap4-iommu";

			reg = <0x55082000 0x100>;

				reg = <0x0 0x100>;

				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "mmu_ipu";

				#iommu-cells = <0>;

				ti,iommu-bus-err-back;

			};

		};



		dmm@4e000000 {

			compatible = "ti,omap5-dmm";