Commit a6c45cf0 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965g 



Avoid confusion between i965g meaning broadwater and the gen4+ chipset
families.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 219adae1

drivers/gpu/drm/i915/i915_debugfs.c

+4 −7
Original line number Diff line number Diff line
@@ -58,13 +58,9 @@ static int i915_capabilities(struct seq_file *m, void *data) 
	seq_printf(m, "gen: %d\n", info->gen);

#define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))

	B(is_mobile);

	B(is_i8xx);

	B(is_i85x);

	B(is_i915g);

	B(is_i9xx);

	B(is_i945gm);

	B(is_i965g);

	B(is_i965gm);

	B(is_g33);

	B(need_gfx_hws);

	B(is_g4x);
@@ -79,6 +75,7 @@ static int i915_capabilities(struct seq_file *m, void *data) 
	B(cursor_needs_physical);

	B(has_overlay);

	B(overlay_needs_physical);

	B(supports_tv);

#undef B



	return 0;
@@ -473,7 +470,7 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) 
	seq_printf(m, "RingHead :  %08x\n", head);

	seq_printf(m, "RingTail :  %08x\n", tail);

	seq_printf(m, "RingSize :  %08lx\n", dev_priv->render_ring.size);

	seq_printf(m, "Acthd :     %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));

	seq_printf(m, "Acthd :     %08x\n", I915_READ(INTEL_INFO(dev)->gen >= 4 ? ACTHD_I965 : ACTHD));



	return 0;

}
@@ -535,7 +532,7 @@ static int i915_error_state(struct seq_file *m, void *unused) 
	seq_printf(m, "  IPEHR: 0x%08x\n", error->ipehr);

	seq_printf(m, "  INSTDONE: 0x%08x\n", error->instdone);

	seq_printf(m, "  ACTHD: 0x%08x\n", error->acthd);

	if (IS_I965G(dev)) {

	if (INTEL_INFO(dev)->gen >= 4) {

		seq_printf(m, "  INSTPS: 0x%08x\n", error->instps);

		seq_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);

	}
@@ -757,7 +754,7 @@ static int i915_sr_status(struct seq_file *m, void *unused) 


	if (IS_IRONLAKE(dev))

		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;

	else if (IS_I965GM(dev) || IS_I945G(dev) || IS_I945GM(dev))

	else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))

		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;

	else if (IS_I915GM(dev))

		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;

drivers/gpu/drm/i915/i915_dma.c

+13 −15
Original line number Diff line number Diff line
@@ -63,7 +63,7 @@ static int i915_init_phys_hws(struct drm_device *dev) 


	memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);



	if (IS_I965G(dev))

	if (INTEL_INFO(dev)->gen >= 4)

		dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &

					     0xf0;
@@ -376,7 +376,7 @@ i915_emit_box(struct drm_device *dev, 
		return -EINVAL;

	}



	if (IS_I965G(dev)) {

	if (INTEL_INFO(dev)->gen >= 4) {

		BEGIN_LP_RING(4);

		OUT_RING(GFX_OP_DRAWRECT_INFO_I965);

		OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
@@ -480,7 +480,7 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev, 


		if (!IS_I830(dev) && !IS_845G(dev)) {

			BEGIN_LP_RING(2);

			if (IS_I965G(dev)) {

			if (INTEL_INFO(dev)->gen >= 4) {

				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);

				OUT_RING(batch->start);

			} else {
@@ -887,12 +887,12 @@ static int 
intel_alloc_mchbar_resource(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;

	int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp_lo, temp_hi = 0;

	u64 mchbar_addr;

	int ret;



	if (IS_I965G(dev))

	if (INTEL_INFO(dev)->gen >= 4)

		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);

	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);

	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
@@ -919,7 +919,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev) 
		return ret;

	}



	if (IS_I965G(dev))

	if (INTEL_INFO(dev)->gen >= 4)

		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,

				       upper_32_bits(dev_priv->mch_res.start));
@@ -933,7 +933,7 @@ static void 
intel_setup_mchbar(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;

	int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp;

	bool enabled;
@@ -970,7 +970,7 @@ static void 
intel_teardown_mchbar(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;

	int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp;



	if (dev_priv->mchbar_need_disable) {
@@ -1012,11 +1012,11 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev, 
{

	unsigned long *gtt;

	unsigned long entry, phys;

	int gtt_bar = IS_I9XX(dev) ? 0 : 1;

	int gtt_bar = IS_GEN2(dev) ? 1 : 0;

	int gtt_offset, gtt_size;



	if (IS_I965G(dev)) {

		if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {

	if (INTEL_INFO(dev)->gen >= 4) {

		if (IS_G4X(dev) || INTEL_INFO(dev)->gen > 4) {

			gtt_offset = 2*1024*1024;

			gtt_size = 2*1024*1024;

		} else {
@@ -1041,10 +1041,8 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev, 
	DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);



	/* Mask out these reserved bits on this hardware. */

	if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||

	    IS_I945G(dev) || IS_I945GM(dev)) {

	if (INTEL_INFO(dev)->gen < 4 && !IS_G33(dev))

		entry &= ~PTE_ADDRESS_MASK_HIGH;

	}



	/* If it's not a mapping type we know, then bail. */

	if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
@@ -1899,7 +1897,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	dev_priv->info = (struct intel_device_info *) flags;



	/* Add register map (needed for suspend/resume) */

	mmio_bar = IS_I9XX(dev) ? 0 : 1;

	mmio_bar = IS_GEN2(dev) ? 1 : 0;

	base = pci_resource_start(dev->pdev, mmio_bar);

	size = pci_resource_len(dev->pdev, mmio_bar);

drivers/gpu/drm/i915/i915_drv.c

+41 −43
Original line number Diff line number Diff line
@@ -61,97 +61,101 @@ extern int intel_agp_enabled; 
	.driver_data = (unsigned long) info }



static const struct intel_device_info intel_i830_info = {

	.gen = 2, .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,

	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

};



static const struct intel_device_info intel_845g_info = {

	.gen = 2, .is_i8xx = 1,

	.gen = 2,

	.has_overlay = 1, .overlay_needs_physical = 1,

};



static const struct intel_device_info intel_i85x_info = {

	.gen = 2, .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1,

	.gen = 2, .is_i85x = 1, .is_mobile = 1,

	.cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

};



static const struct intel_device_info intel_i865g_info = {

	.gen = 2, .is_i8xx = 1,

	.gen = 2,

	.has_overlay = 1, .overlay_needs_physical = 1,

};



static const struct intel_device_info intel_i915g_info = {

	.gen = 3, .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,

	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

};

static const struct intel_device_info intel_i915gm_info = {

	.gen = 3, .is_i9xx = 1,  .is_mobile = 1,

	.gen = 3, .is_mobile = 1,

	.cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.supports_tv = 1,

};

static const struct intel_device_info intel_i945g_info = {

	.gen = 3, .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,

	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

};

static const struct intel_device_info intel_i945gm_info = {

	.gen = 3, .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,

	.gen = 3, .is_i945gm = 1, .is_mobile = 1,

	.has_hotplug = 1, .cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.supports_tv = 1,

};



static const struct intel_device_info intel_i965g_info = {

	.gen = 4, .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1,

	.gen = 4, .is_broadwater = 1,

	.has_hotplug = 1,

	.has_overlay = 1,

};



static const struct intel_device_info intel_i965gm_info = {

	.gen = 4, .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,

	.gen = 4, .is_crestline = 1,

	.is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,

	.has_overlay = 1,

	.supports_tv = 1,

};



static const struct intel_device_info intel_g33_info = {

	.gen = 3, .is_g33 = 1, .is_i9xx = 1,

	.gen = 3, .is_g33 = 1,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.has_overlay = 1,

};



static const struct intel_device_info intel_g45_info = {

	.gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,

	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1,

	.has_pipe_cxsr = 1, .has_hotplug = 1,

};



static const struct intel_device_info intel_gm45_info = {

	.gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1,

	.gen = 4, .is_g4x = 1,

	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,

	.has_pipe_cxsr = 1, .has_hotplug = 1,

	.supports_tv = 1,

};



static const struct intel_device_info intel_pineview_info = {

	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,

	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.has_overlay = 1,

};



static const struct intel_device_info intel_ironlake_d_info = {

	.gen = 5, .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1,

	.gen = 5, .is_ironlake = 1,

	.need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,

};



static const struct intel_device_info intel_ironlake_m_info = {

	.gen = 5, .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,

	.gen = 5, .is_ironlake = 1, .is_mobile = 1,

	.need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,

};



static const struct intel_device_info intel_sandybridge_d_info = {

	.gen = 6, .is_i965g = 1, .is_i9xx = 1,

	.gen = 6,

	.need_gfx_hws = 1, .has_hotplug = 1,

};



static const struct intel_device_info intel_sandybridge_m_info = {

	.gen = 6, .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1,

	.gen = 6, .is_mobile = 1,

	.need_gfx_hws = 1, .has_hotplug = 1,

};
@@ -359,7 +363,6 @@ int i965_reset(struct drm_device *dev, u8 flags) 
	if (need_display)

		i915_save_display(dev);



	if (IS_I965G(dev) || IS_G4X(dev)) {

	/*

	 * Set the domains we want to reset, then the reset bit (bit 0).

	 * Clear the reset bit after a while and wait for hardware status
@@ -382,11 +385,6 @@ int i965_reset(struct drm_device *dev, u8 flags) 
		mutex_unlock(&dev->struct_mutex);

		return -EIO;

	}

	} else {

		DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");

		mutex_unlock(&dev->struct_mutex);

		return -ENODEV;

	}



	/* Ok, now get things going again... */

drivers/gpu/drm/i915/i915_drv.h

+5 −13
Original line number Diff line number Diff line
@@ -196,13 +196,9 @@ struct drm_i915_display_funcs { 
struct intel_device_info {

	u8 gen;

	u8 is_mobile : 1;

	u8 is_i8xx : 1;

	u8 is_i85x : 1;

	u8 is_i915g : 1;

	u8 is_i9xx : 1;

	u8 is_i945gm : 1;

	u8 is_i965g : 1;

	u8 is_i965gm : 1;

	u8 is_g33 : 1;

	u8 need_gfx_hws : 1;

	u8 is_g4x : 1;
@@ -217,6 +213,7 @@ struct intel_device_info { 
	u8 cursor_needs_physical : 1;

	u8 has_overlay : 1;

	u8 overlay_needs_physical : 1;

	u8 supports_tv : 1;

};



enum no_fbc_reason {
@@ -1220,8 +1217,6 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, 
#define IS_I915GM(dev)		((dev)->pci_device == 0x2592)

#define IS_I945G(dev)		((dev)->pci_device == 0x2772)

#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)

#define IS_I965G(dev)		(INTEL_INFO(dev)->is_i965g)

#define IS_I965GM(dev)		(INTEL_INFO(dev)->is_i965gm)

#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)

#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)

#define IS_GM45(dev)		((dev)->pci_device == 0x2A42)
@@ -1233,7 +1228,6 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, 
#define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)

#define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)

#define IS_IRONLAKE(dev)	(INTEL_INFO(dev)->is_ironlake)

#define IS_I9XX(dev)		(INTEL_INFO(dev)->is_i9xx)

#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)



#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
@@ -1251,20 +1245,18 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, 
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte

 * rows, which changed the alignment requirements and fence programming.

 */

#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \

#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \

						      IS_I915GM(dev)))

#define SUPPORTS_DIGITAL_OUTPUTS(dev)	(IS_I9XX(dev) && !IS_PINEVIEW(dev))

#define SUPPORTS_DIGITAL_OUTPUTS(dev)	(!IS_GEN2(dev) && !IS_PINEVIEW(dev))

#define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_IRONLAKE(dev))

#define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_IRONLAKE(dev))

#define SUPPORTS_EDP(dev)		(IS_IRONLAKE_M(dev))

#define SUPPORTS_TV(dev)		(IS_I9XX(dev) && IS_MOBILE(dev) && \

					!IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \

					!IS_GEN6(dev))

#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)

#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)

/* dsparb controlled by hw only */

#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))



#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))

#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)

#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)

#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)

#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)

drivers/gpu/drm/i915/i915_gem.c

+19 −10
Original line number Diff line number Diff line
@@ -1346,14 +1346,14 @@ i915_gem_get_gtt_alignment(struct drm_gem_object *obj) 
	 * Minimum alignment is 4k (GTT page size), but might be greater

	 * if a fence register is needed for the object.

	 */

	if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)

	if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE)

		return 4096;



	/*

	 * Previous chips need to be aligned to the size of the smallest

	 * fence register that can contain the object.

	 */

	if (IS_I9XX(dev))

	if (INTEL_INFO(dev)->gen == 3)

		start = 1024*1024;

	else

		start = 512*1024;
@@ -1660,7 +1660,7 @@ i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) 
	uint32_t flush_domains = 0;



	/* The sampler always gets flushed on i965 (sigh) */

	if (IS_I965G(dev))

	if (INTEL_INFO(dev)->gen >= 4)

		flush_domains |= I915_GEM_DOMAIN_SAMPLER;



	ring->flush(dev, ring,
@@ -2443,7 +2443,7 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj, 
	 * therefore we must wait for any outstanding access to complete

	 * before clearing the fence.

	 */

	if (!IS_I965G(dev)) {

	if (INTEL_INFO(dev)->gen < 4) {

		int ret;



		ret = i915_gem_object_flush_gpu_write_domain(obj, true);
@@ -3893,7 +3893,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, 
		exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;

		exec2_list[i].alignment = exec_list[i].alignment;

		exec2_list[i].offset = exec_list[i].offset;

		if (!IS_I965G(dev))

		if (INTEL_INFO(dev)->gen < 4)

			exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;

		else

			exec2_list[i].flags = 0;
@@ -4614,21 +4614,30 @@ i915_gem_load(struct drm_device *dev) 
	if (!drm_core_check_feature(dev, DRIVER_MODESET))

		dev_priv->fence_reg_start = 3;



	if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

	if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

		dev_priv->num_fence_regs = 16;

	else

		dev_priv->num_fence_regs = 8;



	/* Initialize fence registers to zero */

	if (IS_I965G(dev)) {

	switch (INTEL_INFO(dev)->gen) {

	case 6:

		for (i = 0; i < 16; i++)

			I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);

		break;

	case 5:

	case 4:

		for (i = 0; i < 16; i++)

			I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);

	} else {

		for (i = 0; i < 8; i++)

			I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);

		break;

	case 3:

		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

			for (i = 0; i < 8; i++)

				I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);

	case 2:

		for (i = 0; i < 8; i++)

			I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);

		break;

	}

	i915_gem_detect_bit_6_swizzle(dev);

	init_waitqueue_head(&dev_priv->pending_flip_queue);