Commit a6a51403 authored by Ulrich Hecht's avatar Ulrich Hecht Committed by Geert Uytterhoeven
Browse files

pinctrl: renesas: r8a779a0: Add QSPI pins, groups, and functions 



Add the QSPI0-1 pins, groups and functions to the R8A779A0 (V3U) PFC
driver.

Signed-off-by: default avatarUlrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-11-uli+renesas@fpond.eu


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 30db6781

drivers/pinctrl/renesas/pfc-r8a779a0.c

+72 −0
Original line number Diff line number Diff line
@@ -2377,6 +2377,56 @@ static const unsigned int pwm4_mux[] = { 
	PWM4_MARK,

};



/* - QSPI0 ------------------------------------------------------------------ */

static const unsigned int qspi0_ctrl_pins[] = {

	/* SPCLK, SSL */

	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5),

};

static const unsigned int qspi0_ctrl_mux[] = {

	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,

};

static const unsigned int qspi0_data2_pins[] = {

	/* MOSI_IO0, MISO_IO1 */

	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),

};

static const unsigned int qspi0_data2_mux[] = {

	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,

};

static const unsigned int qspi0_data4_pins[] = {

	/* MOSI_IO0, MISO_IO1, IO2, IO3 */

	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),

	RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),

};

static const unsigned int qspi0_data4_mux[] = {

	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,

	QSPI0_IO2_MARK, QSPI0_IO3_MARK

};



/* - QSPI1 ------------------------------------------------------------------ */

static const unsigned int qspi1_ctrl_pins[] = {

	/* SPCLK, SSL */

	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11),

};

static const unsigned int qspi1_ctrl_mux[] = {

	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,

};

static const unsigned int qspi1_data2_pins[] = {

	/* MOSI_IO0, MISO_IO1 */

	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),

};

static const unsigned int qspi1_data2_mux[] = {

	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,

};

static const unsigned int qspi1_data4_pins[] = {

	/* MOSI_IO0, MISO_IO1, IO2, IO3 */

	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),

	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),

};

static const unsigned int qspi1_data4_mux[] = {

	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,

	QSPI1_IO2_MARK, QSPI1_IO3_MARK

};



/* - SCIF0 ------------------------------------------------------------------ */

static const unsigned int scif0_data_pins[] = {

	/* RX0, TX0 */
@@ -2640,6 +2690,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { 
	SH_PFC_PIN_GROUP(pwm3),

	SH_PFC_PIN_GROUP(pwm4),



	SH_PFC_PIN_GROUP(qspi0_ctrl),

	SH_PFC_PIN_GROUP(qspi0_data2),

	SH_PFC_PIN_GROUP(qspi0_data4),

	SH_PFC_PIN_GROUP(qspi1_ctrl),

	SH_PFC_PIN_GROUP(qspi1_data2),

	SH_PFC_PIN_GROUP(qspi1_data4),



	SH_PFC_PIN_GROUP(scif0_data),

	SH_PFC_PIN_GROUP(scif0_clk),

	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -2916,6 +2973,18 @@ static const char * const pwm4_groups[] = { 
	"pwm4",

};



static const char * const qspi0_groups[] = {

	"qspi0_ctrl",

	"qspi0_data2",

	"qspi0_data4",

};



static const char * const qspi1_groups[] = {

	"qspi1_ctrl",

	"qspi1_data2",

	"qspi1_data4",

};



static const char * const scif0_groups[] = {

	"scif0_data",

	"scif0_clk",
@@ -2995,6 +3064,9 @@ static const struct sh_pfc_function pinmux_functions[] = { 
	SH_PFC_FUNCTION(pwm3),

	SH_PFC_FUNCTION(pwm4),



	SH_PFC_FUNCTION(qspi0),

	SH_PFC_FUNCTION(qspi1),



	SH_PFC_FUNCTION(scif0),

	SH_PFC_FUNCTION(scif1),

	SH_PFC_FUNCTION(scif3),