Commit a6a12811 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/dg2: Wait for SNPS PHY calibration during display init 



Initialization of the PHY is handled by the hardware/firmware, but the
driver should wait up to 25ms for the PHY to report that its calibration
has completed.

Bspec: 49189
Bspec: 50107
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-28-matthew.d.roper@intel.com
parent f82f2563

drivers/gpu/drm/i915/display/intel_display_power.c

+5 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include "intel_pm.h"

#include "intel_pps.h"

#include "intel_sideband.h"

#include "intel_snps_phy.h"

#include "intel_tc.h"

#include "intel_vga.h"
@@ -5901,6 +5902,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, 
	if (DISPLAY_VER(dev_priv) >= 12)

		tgl_bw_buddy_init(dev_priv);



	/* 8. Ensure PHYs have completed calibration and adaptation */

	if (IS_DG2(dev_priv))

		intel_snps_phy_wait_for_calibration(dev_priv);



	if (resume && intel_dmc_has_payload(dev_priv))

		intel_dmc_load_program(dev_priv);

drivers/gpu/drm/i915/display/intel_snps_phy.c

+15 −0
Original line number Diff line number Diff line
@@ -21,6 +21,21 @@ 
 * since it is not handled by the shared DPLL framework as on other platforms.

 */



void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv)

{

	enum phy phy;



	for_each_phy_masked(phy, ~0) {

		if (!intel_phy_is_snps(dev_priv, phy))

			continue;



		if (intel_de_wait_for_clear(dev_priv, ICL_PHY_MISC(phy),

					    DG2_PHY_DP_TX_ACK_MASK, 25))

			DRM_ERROR("SNPS PHY %c failed to calibrate after 25ms.\n",

				  phy);

	}

}



static const u32 dg2_ddi_translations[] = {

	/* VS 0, pre-emph 0 */

	REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26),

drivers/gpu/drm/i915/display/intel_snps_phy.h

+3 −0
Original line number Diff line number Diff line
@@ -8,10 +8,13 @@ 


#include <linux/types.h>



struct drm_i915_private;

struct intel_encoder;

struct intel_crtc_state;

struct intel_mpllb_state;



void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv);



int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,

			   struct intel_encoder *encoder);

void intel_mpllb_enable(struct intel_encoder *encoder,

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -12434,6 +12434,7 @@ enum skl_power_gate { 
						 _ICL_PHY_MISC_B)

#define  ICL_PHY_MISC_MUX_DDID			(1 << 28)

#define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)

#define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23, 20)



/* Icelake Display Stream Compression Registers */

#define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)