Commit a6922f4a authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/xelpd: Add XE_LPD power wells 



Aside from the hardware-managed PG0, XE_LPD has power wells 1-2 and
A-D.  These power wells should be enabled/disabled according to the
following dependency tree (enable top to bottom, disable bottom to top):

               PG0
                |
             --PG1--
            /       \
          PGA     --PG2--
                 /   |   \
               PGB  PGC  PGD

PWR_WELL_CTL follows the general ICL/TGL design and places PG A-D in the
bits that would have been PG 6-9 under the old scheme.

PWR_WELL_CTL_{DDI,AUX}'s bit indexing for DDI's A-C and TC1 is the same
as TGL, but DDI-D is placed at index 7 (bits 14 & 15).

v2:
 - Squash in LPSP status patch from Uma since it's also a
   powerwell-specific change.

Bspec: 49233
Bspec: 49503
Bspec: 49504
Bspec: 49505
Bspec: 49296
Bspec: 50090
Bspec: 53920
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210512042144.2089071-4-matthew.d.roper@intel.com
parent 1649a4cc

drivers/gpu/drm/i915/display/intel_display_debugfs.c

+6 −0
Original line number Diff line number Diff line
@@ -1340,6 +1340,12 @@ static int i915_lpsp_status(struct seq_file *m, void *unused) 
{

	struct drm_i915_private *i915 = node_to_i915(m->private);



	if (DISPLAY_VER(i915) >= 13) {

		LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,

							   SKL_DISP_PW_2));

		return 0;

	}



	switch (DISPLAY_VER(i915)) {

	case 12:

	case 11:

drivers/gpu/drm/i915/display/intel_display_power.c

+423 −1
Original line number Diff line number Diff line
@@ -1042,7 +1042,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 
	enum i915_power_well_id high_pg;



	/* Power wells at this level and above must be disabled for DC5 entry */

	if (DISPLAY_VER(dev_priv) >= 12)

	if (DISPLAY_VER(dev_priv) == 12)

		high_pg = ICL_DISP_PW_3;

	else

		high_pg = SKL_DISP_PW_2;
@@ -3022,6 +3022,113 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, 
	BIT_ULL(POWER_DOMAIN_AUX_B) |			\

	BIT_ULL(POWER_DOMAIN_INIT))



/*

 * XE_LPD Power Domains

 *

 * Previous platforms required that PG(n-1) be enabled before PG(n).  That

 * dependency chain turns into a dependency tree on XE_LPD:

 *

 *       PG0

 *        |

 *     --PG1--

 *    /       \

 *  PGA     --PG2--

 *         /   |   \

 *       PGB  PGC  PGD

 *

 * Power wells must be enabled from top to bottom and disabled from bottom

 * to top.  This allows pipes to be power gated independently.

 */



#define XELPD_PW_D_POWER_DOMAINS (			\

	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\

	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |	\

	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\

	BIT_ULL(POWER_DOMAIN_INIT))



#define XELPD_PW_C_POWER_DOMAINS (			\

	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\

	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\

	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\

	BIT_ULL(POWER_DOMAIN_INIT))



#define XELPD_PW_B_POWER_DOMAINS (			\

	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\

	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\

	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\

	BIT_ULL(POWER_DOMAIN_INIT))



#define XELPD_PW_A_POWER_DOMAINS (			\

	BIT_ULL(POWER_DOMAIN_PIPE_A) |			\

	BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |	\

	BIT_ULL(POWER_DOMAIN_INIT))



#define XELPD_PW_2_POWER_DOMAINS (			\

	XELPD_PW_B_POWER_DOMAINS |			\

	XELPD_PW_C_POWER_DOMAINS |			\

	XELPD_PW_D_POWER_DOMAINS |			\

	BIT_ULL(POWER_DOMAIN_AUDIO) |			\

	BIT_ULL(POWER_DOMAIN_VGA) |			\

	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |	\

	BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) |	\

	BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) |	\

	BIT_ULL(POWER_DOMAIN_AUX_C) |			\

	BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) |	\

	BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) |	\

	BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) |	\

	BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) |	\

	BIT_ULL(POWER_DOMAIN_AUX_C) |			\

	BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) |		\

	BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) |		\

	BIT_ULL(POWER_DOMAIN_AUX_USBC1) |			\

	BIT_ULL(POWER_DOMAIN_AUX_USBC2) |			\

	BIT_ULL(POWER_DOMAIN_AUX_USBC3) |			\

	BIT_ULL(POWER_DOMAIN_AUX_USBC4) |			\

	BIT_ULL(POWER_DOMAIN_INIT))



/*

 * XELPD PW_1/PG_1 domains (under HW/DMC control):

 *  - DBUF function (registers are in PW0)

 *  - Transcoder A

 *  - DDI_A and DDI_B

 *

 * XELPD PW_0/PW_1 domains (under HW/DMC control):

 *  - PCI

 *  - Clocks except port PLL

 *  - Shared functions:

 *     * interrupts except pipe interrupts

 *     * MBus except PIPE_MBUS_DBOX_CTL

 *     * DBUF registers

 *  - Central power except FBC

 *  - Top-level GTC (DDI-level GTC is in the well associated with the DDI)

 */



#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS (		\

	XELPD_PW_2_POWER_DOMAINS |			\

	BIT_ULL(POWER_DOMAIN_MODESET) |			\

	BIT_ULL(POWER_DOMAIN_AUX_A) |			\

	BIT_ULL(POWER_DOMAIN_AUX_B) |			\

	BIT_ULL(POWER_DOMAIN_INIT))



#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS	BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)

#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS	BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)

#define XELPD_AUX_IO_USBC1_POWER_DOMAINS	BIT_ULL(POWER_DOMAIN_AUX_USBC1)

#define XELPD_AUX_IO_USBC2_POWER_DOMAINS	BIT_ULL(POWER_DOMAIN_AUX_USBC2)

#define XELPD_AUX_IO_USBC3_POWER_DOMAINS	BIT_ULL(POWER_DOMAIN_AUX_USBC3)

#define XELPD_AUX_IO_USBC4_POWER_DOMAINS	BIT_ULL(POWER_DOMAIN_AUX_USBC4)



#define XELPD_AUX_IO_TBT1_POWER_DOMAINS		BIT_ULL(POWER_DOMAIN_AUX_TBT1)

#define XELPD_AUX_IO_TBT2_POWER_DOMAINS		BIT_ULL(POWER_DOMAIN_AUX_TBT2)

#define XELPD_AUX_IO_TBT3_POWER_DOMAINS		BIT_ULL(POWER_DOMAIN_AUX_TBT3)

#define XELPD_AUX_IO_TBT4_POWER_DOMAINS		BIT_ULL(POWER_DOMAIN_AUX_TBT4)



#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS	BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D_XELPD)

#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS	BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E_XELPD)

#define XELPD_DDI_IO_TC1_POWER_DOMAINS		BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)

#define XELPD_DDI_IO_TC2_POWER_DOMAINS		BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)

#define XELPD_DDI_IO_TC3_POWER_DOMAINS		BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)

#define XELPD_DDI_IO_TC4_POWER_DOMAINS		BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)



static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {

	.sync_hw = i9xx_power_well_sync_hw_noop,

	.enable = i9xx_always_on_power_well_noop,
@@ -4526,6 +4633,319 @@ static const struct i915_power_well_desc rkl_power_wells[] = { 
	},

};



static const struct i915_power_well_desc xelpd_power_wells[] = {

	{

		.name = "always-on",

		.always_on = true,

		.domains = POWER_DOMAIN_MASK,

		.ops = &i9xx_always_on_power_well_ops,

		.id = DISP_PW_ID_NONE,

	},

	{

		.name = "power well 1",

		/* Handled by the DMC firmware */

		.always_on = true,

		.domains = 0,

		.ops = &hsw_power_well_ops,

		.id = SKL_DISP_PW_1,

		{

			.hsw.regs = &hsw_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_PW_1,

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "DC off",

		.domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,

		.ops = &gen9_dc_off_power_well_ops,

		.id = SKL_DISP_DC_OFF,

	},

	{

		.name = "power well 2",

		.domains = XELPD_PW_2_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = SKL_DISP_PW_2,

		{

			.hsw.regs = &hsw_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_PW_2,

			.hsw.has_vga = true,

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "power well A",

		.domains = XELPD_PW_A_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &hsw_power_well_regs,

			.hsw.idx = XELPD_PW_CTL_IDX_PW_A,

			.hsw.irq_pipe_mask = BIT(PIPE_A),

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "power well B",

		.domains = XELPD_PW_B_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &hsw_power_well_regs,

			.hsw.idx = XELPD_PW_CTL_IDX_PW_B,

			.hsw.irq_pipe_mask = BIT(PIPE_B),

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "power well C",

		.domains = XELPD_PW_C_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &hsw_power_well_regs,

			.hsw.idx = XELPD_PW_CTL_IDX_PW_C,

			.hsw.irq_pipe_mask = BIT(PIPE_C),

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "power well D",

		.domains = XELPD_PW_D_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &hsw_power_well_regs,

			.hsw.idx = XELPD_PW_CTL_IDX_PW_D,

			.hsw.irq_pipe_mask = BIT(PIPE_D),

			.hsw.has_fuses = true,

		},

	},

	{

		.name = "DDI A IO",

		.domains = ICL_DDI_IO_A_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,

		}

	},

	{

		.name = "DDI B IO",

		.domains = ICL_DDI_IO_B_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,

		}

	},

	{

		.name = "DDI C IO",

		.domains = ICL_DDI_IO_C_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_DDI_C,

		}

	},

	{

		.name = "DDI IO D_XELPD",

		.domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = XELPD_PW_CTL_IDX_DDI_D,

		}

	},

	{

		.name = "DDI IO E_XELPD",

		.domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = XELPD_PW_CTL_IDX_DDI_E,

		}

	},

	{

		.name = "DDI IO TC1",

		.domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,

		}

	},

	{

		.name = "DDI IO TC2",

		.domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,

		}

	},

	{

		.name = "DDI IO TC3",

		.domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,

		}

	},

	{

		.name = "DDI IO TC4",

		.domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_ddi_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,

		}

	},

	{

		.name = "AUX A",

		.domains = ICL_AUX_A_IO_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,

		},

	},

	{

		.name = "AUX B",

		.domains = ICL_AUX_B_IO_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,

		},

	},

	{

		.name = "AUX C",

		.domains = TGL_AUX_C_IO_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_AUX_C,

		},

	},

	{

		.name = "AUX D_XELPD",

		.domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = XELPD_PW_CTL_IDX_AUX_D,

		},

	},

	{

		.name = "AUX E_XELPD",

		.domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = XELPD_PW_CTL_IDX_AUX_E,

		},

	},

	{

		.name = "AUX USBC1",

		.domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,

		},

	},

	{

		.name = "AUX USBC2",

		.domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,

		},

	},

	{

		.name = "AUX USBC3",

		.domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,

		},

	},

	{

		.name = "AUX USBC4",

		.domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,

		},

	},

	{

		.name = "AUX TBT1",

		.domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,

			.hsw.is_tc_tbt = true,

		},

	},

	{

		.name = "AUX TBT2",

		.domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,

			.hsw.is_tc_tbt = true,

		},

	},

	{

		.name = "AUX TBT3",

		.domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,

			.hsw.is_tc_tbt = true,

		},

	},

	{

		.name = "AUX TBT4",

		.domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,

		.ops = &icl_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,

			.hsw.is_tc_tbt = true,

		},

	},

};



static int

sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,

				   int disable_power_well)
@@ -4690,6 +5110,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) 
	if (!HAS_DISPLAY(dev_priv)) {

		power_domains->power_well_count = 0;

		err = 0;

	} else if (DISPLAY_VER(dev_priv) >= 13) {

		err = set_power_wells(power_domains, xelpd_power_wells);

	} else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {

		err = set_power_wells_mask(power_domains, tgl_power_wells,

					   BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));

drivers/gpu/drm/i915/display/intel_display_power.h

+9 −0
Original line number Diff line number Diff line
@@ -49,6 +49,9 @@ enum intel_display_power_domain { 
	POWER_DOMAIN_PORT_DDI_LANES_TC5,

	POWER_DOMAIN_PORT_DDI_LANES_TC6,



	POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5, /* XELPD */

	POWER_DOMAIN_PORT_DDI_LANES_E_XELPD,



	POWER_DOMAIN_PORT_DDI_A_IO,

	POWER_DOMAIN_PORT_DDI_B_IO,

	POWER_DOMAIN_PORT_DDI_C_IO,
@@ -66,6 +69,9 @@ enum intel_display_power_domain { 
	POWER_DOMAIN_PORT_DDI_IO_TC5,

	POWER_DOMAIN_PORT_DDI_IO_TC6,



	POWER_DOMAIN_PORT_DDI_IO_D_XELPD = POWER_DOMAIN_PORT_DDI_IO_TC5, /* XELPD */

	POWER_DOMAIN_PORT_DDI_IO_E_XELPD,



	POWER_DOMAIN_PORT_DSI,

	POWER_DOMAIN_PORT_CRT,

	POWER_DOMAIN_PORT_OTHER,
@@ -88,6 +94,9 @@ enum intel_display_power_domain { 
	POWER_DOMAIN_AUX_USBC5,

	POWER_DOMAIN_AUX_USBC6,



	POWER_DOMAIN_AUX_D_XELPD = POWER_DOMAIN_AUX_USBC5, /* XELPD */

	POWER_DOMAIN_AUX_E_XELPD,



	POWER_DOMAIN_AUX_IO_A,

	POWER_DOMAIN_AUX_C_TBT,

	POWER_DOMAIN_AUX_D_TBT,

drivers/gpu/drm/i915/display/intel_vdsc.c

+2 −2
Original line number Diff line number Diff line
@@ -470,13 +470,13 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) 
	 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:

	 *

	 *  - ICL eDP/DSI transcoder

	 *  - Gen12+ (except RKL) pipe A

	 *  - Display version 12 (except RKL) pipe A

	 *

	 * For any other pipe, VDSC/joining uses the power well associated with

	 * the pipe in use. Hence another reference on the pipe power domain

	 * will suffice. (Except no VDSC/joining on ICL pipe A.)

	 */

	if (DISPLAY_VER(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)

	if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)

		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;

	else if (is_pipe_dsc(crtc_state))

		return POWER_DOMAIN_PIPE(pipe);

drivers/gpu/drm/i915/i915_reg.h

+10 −0
Original line number Diff line number Diff line
@@ -9635,6 +9635,12 @@ enum { 
#define   ICL_PW_CTL_IDX_PW_2			1

#define   ICL_PW_CTL_IDX_PW_1			0



/* XE_LPD - power wells */

#define   XELPD_PW_CTL_IDX_PW_D			8

#define   XELPD_PW_CTL_IDX_PW_C			7

#define   XELPD_PW_CTL_IDX_PW_B			6

#define   XELPD_PW_CTL_IDX_PW_A			5



#define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)

#define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)

#define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
@@ -9649,7 +9655,9 @@ enum { 
#define   TGL_PW_CTL_IDX_AUX_TBT1		9

#define   ICL_PW_CTL_IDX_AUX_TBT1		8

#define   TGL_PW_CTL_IDX_AUX_TC6		8

#define   XELPD_PW_CTL_IDX_AUX_E			8

#define   TGL_PW_CTL_IDX_AUX_TC5		7

#define   XELPD_PW_CTL_IDX_AUX_D			7

#define   TGL_PW_CTL_IDX_AUX_TC4		6

#define   ICL_PW_CTL_IDX_AUX_F			5

#define   TGL_PW_CTL_IDX_AUX_TC3		5
@@ -9664,7 +9672,9 @@ enum { 
#define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)

#define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)

#define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)

#define   XELPD_PW_CTL_IDX_DDI_E			8

#define   TGL_PW_CTL_IDX_DDI_TC6		8

#define   XELPD_PW_CTL_IDX_DDI_D			7

#define   TGL_PW_CTL_IDX_DDI_TC5		7

#define   TGL_PW_CTL_IDX_DDI_TC4		6

#define   ICL_PW_CTL_IDX_DDI_F			5