Commit a689702a authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue 



Tony Nguyen says:

====================
Intel Wired LAN Driver Updates 2021-10-20

This series contains updates to e1000e, igc, and ice drivers.

Sasha fixes an issue with dropped packets on Tiger Lake platforms for
e1000e and corrects a device ID for igc.

Tony adds missing E810 device IDs for ice.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 4225fea1 7dcf78b8

drivers/net/ethernet/intel/e1000e/e1000.h

+3 −1
Original line number Diff line number Diff line
@@ -113,7 +113,8 @@ enum e1000_boards { 
	board_pch2lan,

	board_pch_lpt,

	board_pch_spt,

	board_pch_cnp

	board_pch_cnp,

	board_pch_tgp

};



struct e1000_ps_page {
@@ -499,6 +500,7 @@ extern const struct e1000_info e1000_pch2_info; 
extern const struct e1000_info e1000_pch_lpt_info;

extern const struct e1000_info e1000_pch_spt_info;

extern const struct e1000_info e1000_pch_cnp_info;

extern const struct e1000_info e1000_pch_tgp_info;

extern const struct e1000_info e1000_es2_info;



void e1000e_ptp_init(struct e1000_adapter *adapter);

drivers/net/ethernet/intel/e1000e/ich8lan.c

+30 −1
Original line number Diff line number Diff line
@@ -4813,7 +4813,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 
static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)

{

	struct e1000_mac_info *mac = &hw->mac;

	u32 ctrl_ext, txdctl, snoop;

	u32 ctrl_ext, txdctl, snoop, fflt_dbg;

	s32 ret_val;

	u16 i;
@@ -4872,6 +4872,15 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 
		snoop = (u32)~(PCIE_NO_SNOOP_ALL);

	e1000e_set_pcie_no_snoop(hw, snoop);



	/* Enable workaround for packet loss issue on TGP PCH

	 * Do not gate DMA clock from the modPHY block

	 */

	if (mac->type >= e1000_pch_tgp) {

		fflt_dbg = er32(FFLT_DBG);

		fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK;

		ew32(FFLT_DBG, fflt_dbg);

	}



	ctrl_ext = er32(CTRL_EXT);

	ctrl_ext |= E1000_CTRL_EXT_RO_DIS;

	ew32(CTRL_EXT, ctrl_ext);
@@ -5992,3 +6001,23 @@ const struct e1000_info e1000_pch_cnp_info = { 
	.phy_ops		= &ich8_phy_ops,

	.nvm_ops		= &spt_nvm_ops,

};



const struct e1000_info e1000_pch_tgp_info = {

	.mac			= e1000_pch_tgp,

	.flags			= FLAG_IS_ICH

				  | FLAG_HAS_WOL

				  | FLAG_HAS_HW_TIMESTAMP

				  | FLAG_HAS_CTRLEXT_ON_LOAD

				  | FLAG_HAS_AMT

				  | FLAG_HAS_FLASH

				  | FLAG_HAS_JUMBO_FRAMES

				  | FLAG_APME_IN_WUC,

	.flags2			= FLAG2_HAS_PHY_STATS

				  | FLAG2_HAS_EEE,

	.pba			= 26,

	.max_hw_frame_size	= 9022,

	.get_variants		= e1000_get_variants_ich8lan,

	.mac_ops		= &ich8_mac_ops,

	.phy_ops		= &ich8_phy_ops,

	.nvm_ops		= &spt_nvm_ops,

};

drivers/net/ethernet/intel/e1000e/ich8lan.h

+3 −0
Original line number Diff line number Diff line
@@ -289,6 +289,9 @@ 
/* Proprietary Latency Tolerance Reporting PCI Capability */

#define E1000_PCI_LTR_CAP_LPT		0xA8



/* Don't gate wake DMA clock */

#define E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK	0x1000



void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);

void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,

						  bool state);

drivers/net/ethernet/intel/e1000e/netdev.c

+23 −22
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ static const struct e1000_info *e1000_info_tbl[] = { 
	[board_pch_lpt]		= &e1000_pch_lpt_info,

	[board_pch_spt]		= &e1000_pch_spt_info,

	[board_pch_cnp]		= &e1000_pch_cnp_info,

	[board_pch_tgp]		= &e1000_pch_tgp_info,

};



struct e1000_reg_info {
@@ -7896,28 +7897,28 @@ static const struct pci_device_id e1000_pci_tbl[] = { 
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM19), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V19), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_cnp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM19), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V19), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_tgp },

	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_tgp },



	{ 0, 0, 0, 0, 0, 0, 0 }	/* terminate list */

};

drivers/net/ethernet/intel/ice/ice_common.c

+2 −0
Original line number Diff line number Diff line
@@ -25,6 +25,8 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw) 
	case ICE_DEV_ID_E810C_BACKPLANE:

	case ICE_DEV_ID_E810C_QSFP:

	case ICE_DEV_ID_E810C_SFP:

	case ICE_DEV_ID_E810_XXV_BACKPLANE:

	case ICE_DEV_ID_E810_XXV_QSFP:

	case ICE_DEV_ID_E810_XXV_SFP:

		hw->mac_type = ICE_MAC_E810;

		break;