Commit a684cb41 authored by Sebastian Reichel's avatar Sebastian Reichel Committed by Heiko Stuebner
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arm64: dts: rockchip: add USB2 support for rk3588 



This adds USB2 (EHCI & OHCI) ports including the related PHYs
and GRF modules to the rk3588(s) device tree.

Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230712165106.65603-2-sebastian.reichel@collabora.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 9b9fb10b

arch/arm64/boot/dts/rockchip/rk3588s.dtsi

+94 −0
Original line number Diff line number Diff line
@@ -399,6 +399,50 @@ 
		};

	};



	usb_host0_ehci: usb@fc800000 {

		compatible = "rockchip,rk3588-ehci", "generic-ehci";

		reg = <0x0 0xfc800000 0x0 0x40000>;

		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;

		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;

		phys = <&u2phy2_host>;

		phy-names = "usb";

		power-domains = <&power RK3588_PD_USB>;

		status = "disabled";

	};



	usb_host0_ohci: usb@fc840000 {

		compatible = "rockchip,rk3588-ohci", "generic-ohci";

		reg = <0x0 0xfc840000 0x0 0x40000>;

		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;

		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;

		phys = <&u2phy2_host>;

		phy-names = "usb";

		power-domains = <&power RK3588_PD_USB>;

		status = "disabled";

	};



	usb_host1_ehci: usb@fc880000 {

		compatible = "rockchip,rk3588-ehci", "generic-ehci";

		reg = <0x0 0xfc880000 0x0 0x40000>;

		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;

		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;

		phys = <&u2phy3_host>;

		phy-names = "usb";

		power-domains = <&power RK3588_PD_USB>;

		status = "disabled";

	};



	usb_host1_ohci: usb@fc8c0000 {

		compatible = "rockchip,rk3588-ohci", "generic-ohci";

		reg = <0x0 0xfc8c0000 0x0 0x40000>;

		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;

		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;

		phys = <&u2phy3_host>;

		phy-names = "usb";

		power-domains = <&power RK3588_PD_USB>;

		status = "disabled";

	};



	sys_grf: syscon@fd58c000 {

		compatible = "rockchip,rk3588-sys-grf", "syscon";

		reg = <0x0 0xfd58c000 0x0 0x1000>;
@@ -419,6 +463,56 @@ 
		reg = <0x0 0xfd5c4000 0x0 0x100>;

	};



	usb2phy2_grf: syscon@fd5d8000 {

		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";

		reg = <0x0 0xfd5d8000 0x0 0x4000>;

		#address-cells = <1>;

		#size-cells = <1>;



		u2phy2: usb2-phy@8000 {

			compatible = "rockchip,rk3588-usb2phy";

			reg = <0x8000 0x10>;

			interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;

			resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;

			reset-names = "phy", "apb";

			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;

			clock-names = "phyclk";

			clock-output-names = "usb480m_phy2";

			#clock-cells = <0>;

			status = "disabled";



			u2phy2_host: host-port {

				#phy-cells = <0>;

				status = "disabled";

			};

		};

	};



	usb2phy3_grf: syscon@fd5dc000 {

		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";

		reg = <0x0 0xfd5dc000 0x0 0x4000>;

		#address-cells = <1>;

		#size-cells = <1>;



		u2phy3: usb2-phy@c000 {

			compatible = "rockchip,rk3588-usb2phy";

			reg = <0xc000 0x10>;

			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;

			resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;

			reset-names = "phy", "apb";

			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;

			clock-names = "phyclk";

			clock-output-names = "usb480m_phy3";

			#clock-cells = <0>;

			status = "disabled";



			u2phy3_host: host-port {

				#phy-cells = <0>;

				status = "disabled";

			};

		};

	};



	ioc: syscon@fd5f0000 {

		compatible = "rockchip,rk3588-ioc", "syscon";

		reg = <0x0 0xfd5f0000 0x0 0x10000>;