Commit a6772153 authored by Kai Ye's avatar Kai Ye Committed by Zheng Zengkai
Browse files

crypto: hisilicon/sec - only HW V2 needs to change the BD err detection 

mainline inclusion
from mainline-master
commit bffa1fc0
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5MK7S
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bffa1fc06589



----------------------------------------------------------------------

The base register address of V2 and V3 are different. HW V3 not needs
to change the BD err detection.

Signed-off-by: default avatarKai Ye <yekai13@huawei.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: default avatarJiangshui Yang <yangjiangshui@h-partners.com>
Reviewed-by: default avatarXiu Jianfeng <xiujianfeng@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 62efb773

drivers/crypto/hisilicon/sec2/sec_main.c

+8 −7
Original line number Diff line number Diff line
@@ -508,16 +508,17 @@ static int sec_engine_init(struct hisi_qm *qm) 


	writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG);



	if (qm->ver < QM_HW_V3) {

		/* HW V2 enable sm4 extra mode, as ctr/ecb */

	if (qm->ver < QM_HW_V3)

		writel_relaxed(SEC_BD_ERR_CHK_EN0,

			       qm->io_base + SEC_BD_ERR_CHK_EN_REG0);



	/* Enable sm4 xts mode multiple iv */

		/* HW V2 enable sm4 xts mode multiple iv */

		writel_relaxed(SEC_BD_ERR_CHK_EN1,

			       qm->io_base + SEC_BD_ERR_CHK_EN_REG1);

		writel_relaxed(SEC_BD_ERR_CHK_EN3,

			       qm->io_base + SEC_BD_ERR_CHK_EN_REG3);

	}



	/* config endian */

	sec_set_endian(qm);