Commit a673dae8 authored by Claudiu Beznea's avatar Claudiu Beznea
Browse files

clk: at91: clk-sam9x60-pll: add support for parent_hw 



Add support for parent_hw in SAM9X60 PLL clock drivers.
With this parent-child relation is described with pointers rather
than strings making registration a bit faster.

All the SoC based drivers that rely on clk-sam9x60-pll were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: default avatarMaxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20230615093227.576102-9-claudiu.beznea@microchip.com
parent 077782e3

drivers/clk/at91/clk-sam9x60-pll.c

+12 −5
Original line number Diff line number Diff line
@@ -616,7 +616,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, 
{

	struct sam9x60_frac *frac;

	struct clk_hw *hw;

	struct clk_init_data init;

	struct clk_init_data init = {};

	unsigned long parent_rate, irqflags;

	unsigned int val;

	int ret;
@@ -629,7 +629,10 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, 
		return ERR_PTR(-ENOMEM);



	init.name = name;

	if (parent_name)

		init.parent_names = &parent_name;

	else

		init.parent_hws = (const struct clk_hw **)&parent_hw;

	init.num_parents = 1;

	if (flags & CLK_SET_RATE_GATE)

		init.ops = &sam9x60_frac_pll_ops;
@@ -692,14 +695,15 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, 


struct clk_hw * __init

sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,

			     const char *name, const char *parent_name, u8 id,

			     const char *name, const char *parent_name,

			     struct clk_hw *parent_hw, u8 id,

			     const struct clk_pll_characteristics *characteristics,

			     const struct clk_pll_layout *layout, u32 flags,

			     u32 safe_div)

{

	struct sam9x60_div *div;

	struct clk_hw *hw;

	struct clk_init_data init;

	struct clk_init_data init = {};

	unsigned long irqflags;

	unsigned int val;

	int ret;
@@ -716,6 +720,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, 
		return ERR_PTR(-ENOMEM);



	init.name = name;

	if (parent_hw)

		init.parent_hws = (const struct clk_hw **)&parent_hw;

	else

		init.parent_names = &parent_name;

	init.num_parents = 1;

	if (flags & CLK_SET_RATE_GATE)

drivers/clk/at91/pmc.h

+2 −1
Original line number Diff line number Diff line
@@ -220,7 +220,8 @@ at91_clk_register_plldiv(struct regmap *regmap, const char *name, 


struct clk_hw * __init

sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,

			     const char *name, const char *parent_name, u8 id,

			     const char *name, const char *parent_name,

			     struct clk_hw *parent_hw, u8 id,

			     const struct clk_pll_characteristics *characteristics,

			     const struct clk_pll_layout *layout, u32 flags,

			     u32 safe_div);

drivers/clk/at91/sam9x60.c

+2 −2
Original line number Diff line number Diff line
@@ -246,7 +246,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) 
		goto err_free;



	hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck",

					  "pllack_fracck", 0, &plla_characteristics,

					  "pllack_fracck", NULL, 0, &plla_characteristics,

					  &pll_div_layout,

					   /*

					    * This feeds CPU. It should not
@@ -266,7 +266,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) 
		goto err_free;



	hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck",

					  "upllck_fracck", 1, &upll_characteristics,

					  "upllck_fracck", NULL, 1, &upll_characteristics,

					  &pll_div_layout,

					  CLK_SET_RATE_GATE |

					  CLK_SET_PARENT_GATE |

drivers/clk/at91/sama7g5.c

+1 −1
Original line number Diff line number Diff line
@@ -975,7 +975,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) 
			case PLL_TYPE_DIV:

				hw = sam9x60_clk_register_div_pll(regmap,

					&pmc_pll_lock, sama7g5_plls[i][j].n,

					sama7g5_plls[i][j].p, i,

					sama7g5_plls[i][j].p, NULL, i,

					sama7g5_plls[i][j].c,

					sama7g5_plls[i][j].l,

					sama7g5_plls[i][j].f,