Commit a667e4d3 authored by Yanteng Si's avatar Yanteng Si Committed by Huacai Chen
Browse files

docs/LoongArch: Fix notes rendering by using reST directives 



Notes are better expressed with reST admonitions.

Fixes: 0ea8ce61 ("Documentation: LoongArch: Add basic documentations")
Reviewed-by: default avatarWANG Xuerui <git@xen0n.name>
Signed-off-by: default avatarYanteng Si <siyanteng@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent b672332e

Documentation/loongarch/introduction.rst

+9 −6
Original line number Diff line number Diff line
@@ -45,10 +45,12 @@ Name Alias Usage Preserved 
``$r23``-``$r31`` ``$s0``-``$s8`` Static registers    Yes

================= =============== =================== ============



Note: The register ``$r21`` is reserved in the ELF psABI, but used by the Linux

kernel for storing the percpu base address. It normally has no ABI name, but is

called ``$u0`` in the kernel. You may also see ``$v0`` or ``$v1`` in some old code,

however they are deprecated aliases of ``$a0`` and ``$a1`` respectively.

.. Note::

    The register ``$r21`` is reserved in the ELF psABI, but used by the Linux

    kernel for storing the percpu base address. It normally has no ABI name,

    but is called ``$u0`` in the kernel. You may also see ``$v0`` or ``$v1``

    in some old code,however they are deprecated aliases of ``$a0`` and ``$a1``

    respectively.



FPRs

----
@@ -69,8 +71,9 @@ Name Alias Usage Preserved 
``$f24``-``$f31`` ``$fs0``-``$fs7``  Static registers    Yes

================= ================== =================== ============



Note: You may see ``$fv0`` or ``$fv1`` in some old code, however they are deprecated

aliases of ``$fa0`` and ``$fa1`` respectively.

.. Note::

    You may see ``$fv0`` or ``$fv1`` in some old code, however they are

    deprecated aliases of ``$fa0`` and ``$fa1`` respectively.



VRs

----

Documentation/loongarch/irq-chip-model.rst

+13 −9
Original line number Diff line number Diff line
@@ -145,12 +145,16 @@ Documentation of Loongson's LS7A chipset: 


  https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English)



Note: CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described

in Section 7.4 of "LoongArch Reference Manual, Vol 1"; LIOINTC is "Legacy I/O

Interrupts" described in Section 11.1 of "Loongson 3A5000 Processor Reference

Manual"; EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of

"Loongson 3A5000 Processor Reference Manual"; HTVECINTC is "HyperTransport

Interrupts" described in Section 14.3 of "Loongson 3A5000 Processor Reference

Manual"; PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of

"Loongson 7A1000 Bridge User Manual"; PCH-LPC is "LPC Interrupts" described in

Section 24.3 of "Loongson 7A1000 Bridge User Manual".
 
.. Note::

    - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described

      in Section 7.4 of "LoongArch Reference Manual, Vol 1";

    - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of

      "Loongson 3A5000 Processor Reference Manual";

    - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of

      "Loongson 3A5000 Processor Reference Manual";

    - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of

      "Loongson 3A5000 Processor Reference Manual";

    - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of

      "Loongson 7A1000 Bridge User Manual";

    - PCH-LPC is "LPC Interrupts" described in Section 24.3 of

      "Loongson 7A1000 Bridge User Manual".