Commit a6610435 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: Handle 32bit CNTPCTSS traps 



When CNTPOFF isn't implemented and that we have a non-zero counter
offset, CNTPCT and CNTPCTSS are trapped. We properly handle the
former, but not the latter, as it is not present in the sysreg
table (despite being actually handled in the code). Bummer.

Just populate the cp15_64 table with the missing register.

Reported-by: default avatarReiji Watanabe <reijiw@google.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 2fe9e0fc

arch/arm64/include/asm/sysreg.h

+1 −0
Original line number Diff line number Diff line
@@ -403,6 +403,7 @@ 
#define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)

#define SYS_AARCH32_CNTPCT		sys_reg(0, 0, 0, 14, 0)

#define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)

#define SYS_AARCH32_CNTPCTSS		sys_reg(0, 8, 0, 14, 0)



#define __PMEV_op2(n)			((n) & 0x7)

#define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))

arch/arm64/kvm/sys_regs.c

+1 −0
Original line number Diff line number Diff line
@@ -2538,6 +2538,7 @@ static const struct sys_reg_desc cp15_64_regs[] = { 
	{ Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */

	{ Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */

	{ SYS_DESC(SYS_AARCH32_CNTP_CVAL),    access_arch_timer },

	{ SYS_DESC(SYS_AARCH32_CNTPCTSS),     access_arch_timer },

};



static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,