Commit a65dbf7c authored by Prike Liang's avatar Prike Liang Committed by Alex Deucher
Browse files

drm/amdgpu/gfx10: Add GC 10.3.7 Support 



Needed to properly initialize GC 10.3.7.

Signed-off-by: default avatarPrike Liang <Prike.Liang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 79aa0367

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+5 −0
Original line number Diff line number Diff line
@@ -1424,6 +1424,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(10, 3, 4):

	case IP_VERSION(10, 3, 5):

	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 7):

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		break;

	default:
@@ -1766,6 +1767,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(10, 3, 3):

		adev->family = AMDGPU_FAMILY_YC;

		break;

	case IP_VERSION(10, 3, 7):

		adev->family = AMDGPU_FAMILY_GC_10_3_7;

		break;

	default:

		return -EINVAL;

	}
@@ -1778,6 +1782,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(10, 1, 4):

	case IP_VERSION(10, 3, 1):

	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 7):

		adev->flags |= AMD_IS_APU;

		break;

	default:

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+52 −1
Original line number Diff line number Diff line
@@ -258,6 +258,13 @@ MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 
MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");

MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");



MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");

MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");

MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");

MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");

MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");

MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");



static const struct soc15_reg_golden golden_settings_gc_10_1[] =

{

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@@ -3408,6 +3415,31 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)

};



static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)

};



#define DEFAULT_SH_MEM_CONFIG \

	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \

	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -3646,6 +3678,11 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 
						golden_settings_gc_10_0_cyan_skillfish,

						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));

		break;

	case IP_VERSION(10, 3, 7):

		soc15_program_register_sequence(adev,

						golden_settings_gc_10_3_7,

						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));

		break;

	default:

		break;

	}
@@ -3835,6 +3872,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 
	case IP_VERSION(10, 3, 4):

	case IP_VERSION(10, 3, 5):

	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 7):

		adev->gfx.cp_fw_write_wait = true;

		break;

	default:
@@ -3962,6 +4000,9 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 
		else

			chip_name = "cyan_skillfish";

		break;

	case IP_VERSION(10, 3, 7):

		chip_name = "gc_10_3_7";

		break;

	default:

		BUG();

	}
@@ -4558,6 +4599,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 
	case IP_VERSION(10, 3, 4):

	case IP_VERSION(10, 3, 5):

	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 7):

		adev->gfx.config.max_hw_contexts = 8;

		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4695,6 +4737,7 @@ static int gfx_v10_0_sw_init(void *handle) 
	case IP_VERSION(10, 3, 4):

	case IP_VERSION(10, 3, 5):

	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 7):

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 1;

		adev->gfx.me.num_queue_per_pipe = 1;
@@ -6207,6 +6250,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 
	case IP_VERSION(10, 3, 4):

	case IP_VERSION(10, 3, 5):

	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 7):

		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

				    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);

		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
@@ -6344,6 +6388,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 
		case IP_VERSION(10, 3, 4):

		case IP_VERSION(10, 3, 5):

		case IP_VERSION(10, 3, 3):

		case IP_VERSION(10, 3, 7):

			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);

			break;

		default:
@@ -6358,6 +6403,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 
		case IP_VERSION(10, 3, 4):

		case IP_VERSION(10, 3, 5):

		case IP_VERSION(10, 3, 3):

		case IP_VERSION(10, 3, 7):

			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,

				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |

				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
@@ -7185,6 +7231,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 
		break;

	case IP_VERSION(10, 3, 1):

	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 7):

		return true;

	default:

		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
@@ -7220,6 +7267,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 
	case IP_VERSION(10, 3, 4):

	case IP_VERSION(10, 3, 5):

	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 7):

		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */

		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<

			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
@@ -7672,6 +7720,7 @@ static int gfx_v10_0_early_init(void *handle) 
	case IP_VERSION(10, 3, 4):

	case IP_VERSION(10, 3, 5):

	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 7):

		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;

		break;

	default:
@@ -9430,6 +9479,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 
	case IP_VERSION(10, 3, 4):

	case IP_VERSION(10, 3, 5):

	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 7):

		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;

		break;

	case IP_VERSION(10, 1, 2):
@@ -9522,7 +9572,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 
		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

			bitmap = i * adev->gfx.config.max_sh_per_se + j;

			if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||

				(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&

				(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||

				(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&

			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))

				continue;

			mask = 1;

include/uapi/drm/amdgpu_drm.h

+1 −0
Original line number Diff line number Diff line
@@ -1151,6 +1151,7 @@ struct drm_amdgpu_info_video_caps { 
#define AMDGPU_FAMILY_NV			143 /* Navi10 */

#define AMDGPU_FAMILY_VGH			144 /* Van Gogh */

#define AMDGPU_FAMILY_YC			146 /* Yellow Carp */

#define AMDGPU_FAMILY_GC_10_3_7			151 /* GC 10.3.7 */



#if defined(__cplusplus)

}