Commit a659f2fd authored by Wesley Chalmers's avatar Wesley Chalmers Committed by Alex Deucher
Browse files

drm/amd/display: Add interface to get Calibrated Avg Level from FIFO 



[WHY]
Hardware has handed down a new sequence requiring the value of this
register be read from clk_mgr.

Signed-off-by: default avatarWesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarAnson Jacob <Anson.Jacob@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9cf9498f

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

+24 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
	SRI(AFMT_60958_1, DIG, id), \

	SRI(AFMT_60958_2, DIG, id), \

	SRI(DIG_FE_CNTL, DIG, id), \

	SRI(DIG_FIFO_STATUS, DIG, id), \

	SRI(HDMI_CONTROL, DIG, id), \

	SRI(HDMI_DB_CONTROL, DIG, id), \

	SRI(HDMI_GC, DIG, id), \
@@ -124,6 +125,7 @@ struct dcn10_stream_enc_registers { 
	uint32_t AFMT_60958_2;

	uint32_t DIG_FE_CNTL;

	uint32_t DIG_FE_CNTL2;

	uint32_t DIG_FIFO_STATUS;

	uint32_t DP_MSE_RATE_CNTL;

	uint32_t DP_MSE_RATE_UPDATE;

	uint32_t DP_PIXEL_FORMAT;
@@ -266,6 +268,17 @@ struct dcn10_stream_enc_registers { 
	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\

	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\

	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\

	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\

	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\

	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
@@ -488,6 +501,17 @@ struct dcn10_stream_enc_registers { 
	type DP_VID_N_MUL;\

	type DP_VID_M_DOUBLE_VALUE_EN;\

	type DIG_SOURCE_SELECT;\

	type DIG_FIFO_LEVEL_ERROR;\

	type DIG_FIFO_USE_OVERWRITE_LEVEL;\

	type DIG_FIFO_OVERWRITE_LEVEL;\

	type DIG_FIFO_ERROR_ACK;\

	type DIG_FIFO_CAL_AVERAGE_LEVEL;\

	type DIG_FIFO_MAXIMUM_LEVEL;\

	type DIG_FIFO_MINIMUM_LEVEL;\

	type DIG_FIFO_READ_CLOCK_SRC;\

	type DIG_FIFO_CALIBRATED;\

	type DIG_FIFO_FORCE_RECAL_AVERAGE;\

	type DIG_FIFO_FORCE_RECOMP_MINMAX;\

	type DIG_CLOCK_PATTERN



#define SE_REG_FIELD_LIST_DCN2_0(type) \

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c

+12 −0
Original line number Diff line number Diff line
@@ -552,6 +552,17 @@ void enc2_stream_encoder_dp_set_stream_attribute( 
		DP_SST_SDP_SPLITTING, enable_sdp_splitting);

}



uint32_t enc2_get_fifo_cal_average_level(

		struct stream_encoder *enc)

{

	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);

	uint32_t fifo_level;



	REG_GET(DIG_FIFO_STATUS,

			DIG_FIFO_CAL_AVERAGE_LEVEL, &fifo_level);

	return fifo_level;

}



static const struct stream_encoder_funcs dcn20_str_enc_funcs = {

	.dp_set_odm_combine =

		enc2_dp_set_odm_combine,
@@ -598,6 +609,7 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = { 
	.dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet,

	.set_dynamic_metadata = enc2_set_dynamic_metadata,

	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,

	.get_fifo_cal_average_level = enc2_get_fifo_cal_average_level,

};



void dcn20_stream_encoder_construct(

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h

+3 −0
Original line number Diff line number Diff line
@@ -112,4 +112,7 @@ void enc2_set_dynamic_metadata(struct stream_encoder *enc, 
		uint32_t hubp_requestor_id,

		enum dynamic_metadata_mode dmdata_mode);



uint32_t enc2_get_fifo_cal_average_level(

		struct stream_encoder *enc);



#endif /* __DC_STREAM_ENCODER_DCN20_H__ */

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c

+2 −0
Original line number Diff line number Diff line
@@ -823,6 +823,8 @@ static const struct stream_encoder_funcs dcn30_str_enc_funcs = { 
	.dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,

	.set_dynamic_metadata = enc2_set_dynamic_metadata,

	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,



	.get_fifo_cal_average_level = enc2_get_fifo_cal_average_level,

};



void dcn30_dio_stream_encoder_construct(

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h

+12 −0
Original line number Diff line number Diff line
@@ -106,6 +106,7 @@ 
	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \

	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \

	SRI(DIG_FE_CNTL, DIG, id), \

	SRI(DIG_FIFO_STATUS, DIG, id), \

	SRI(DIG_CLOCK_PATTERN, DIG, id)
@@ -167,6 +168,17 @@ 
	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\

	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\

	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\

	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\

	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\

	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\

	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\