Commit a656de59 authored by Chang S. Bae's avatar Chang S. Bae Committed by Wentao Guan
Browse files

x86/microcode/intel: Remove unnecessary cache writeback and invalidation 

stable inclusion
from stable-v6.6.81
commit d31d50b35d35147d5dc574453eb6c8c751c6e701
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IBYZED

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=d31d50b35d35147d5dc574453eb6c8c751c6e701



--------------------------------

commit 9a819753b0209c6edebdea447a1aa53e8c697653 upstream

Currently, an unconditional cache flush is performed during every
microcode update. Although the original changelog did not mention
a specific erratum, this measure was primarily intended to address
a specific microcode bug, the load of which has already been blocked by
is_blacklisted(). Therefore, this cache flush is no longer necessary.

Additionally, the side effects of doing this have been overlooked. It
increases CPU rendezvous time during late loading, where the cache flush
takes between 1x to 3.5x longer than the actual microcode update.

Remove native_wbinvd() and update the erratum name to align with the
latest errata documentation, document ID 334163 Version 022US.

  [ bp: Zap the flaky documentation URL. ]

Fixes: 91df9fdf ("x86/microcode/intel: Writeback and invalidate caches before updating microcode")
Reported-by: default avatarYan Hua Wu <yanhua1.wu@intel.com>
Reported-by: default avatarWilliam Xie <william.xie@intel.com>
Signed-off-by: default avatarChang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Acked-by: default avatarAshok Raj <ashok.raj@intel.com>
Tested-by: default avatarYan Hua Wu <yanhua1.wu@intel.com>
Link: https://lore.kernel.org/r/20241001161042.465584-2-chang.seok.bae@intel.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit d31d50b35d35147d5dc574453eb6c8c751c6e701)
Signed-off-by: default avatarWentao Guan <guanwentao@uniontech.com>
parent f95d774d

arch/x86/kernel/cpu/microcode/intel.c

+2 −8
Original line number Diff line number Diff line
@@ -319,12 +319,6 @@ static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci, 
		return UCODE_OK;

	}



	/*

	 * Writeback and invalidate caches before updating microcode to avoid

	 * internal issues depending on what the microcode is updating.

	 */

	native_wbinvd();



	/* write microcode via MSR 0x79 */

	native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
@@ -583,7 +577,7 @@ static bool is_blacklisted(unsigned int cpu) 
	/*

	 * Late loading on model 79 with microcode revision less than 0x0b000021

	 * and LLC size per core bigger than 2.5MB may result in a system hang.

	 * This behavior is documented in item BDF90, #334165 (Intel Xeon

	 * This behavior is documented in item BDX90, #334165 (Intel Xeon

	 * Processor E7-8800/4800 v4 Product Family).

	 */

	if (c->x86 == 6 &&
@@ -591,7 +585,7 @@ static bool is_blacklisted(unsigned int cpu) 
	    c->x86_stepping == 0x01 &&

	    llc_size_per_core > 2621440 &&

	    c->microcode < 0x0b000021) {

		pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);

		pr_err_once("Erratum BDX90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);

		pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS update.\n");

		return true;

	}