Commit a6135dde authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Disable MALL when TMZ surface 



[Description]
- Don't use MALL buffering of any kind when the
  surface is TMZ
- Workaround for a HW bug

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c02e6444

drivers/gpu/drm/amd/display/dc/core/dc.c

+6 −2
Original line number Diff line number Diff line
@@ -2322,9 +2322,13 @@ static enum surface_update_type det_surface_update(const struct dc *dc, 
	type = get_scaling_info_update_type(u);

	elevate_update_type(&overall_type, type);



	if (u->flip_addr)

	if (u->flip_addr) {

		update_flags->bits.addr_update = 1;



		if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) {

			update_flags->bits.tmz_changed = 1;

			elevate_update_type(&overall_type, UPDATE_TYPE_FULL);

		}

	}

	if (u->in_transfer_func)

		update_flags->bits.in_transfer_func_change = 1;

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -1120,6 +1120,7 @@ union surface_update_flags { 
		uint32_t clock_change:1;

		uint32_t stereo_format_change:1;

		uint32_t lut_3d:1;

		uint32_t tmz_changed:1;

		uint32_t full_update:1;

	} bits;

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

+10 −8
Original line number Diff line number Diff line
@@ -369,7 +369,7 @@ bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 
	union dmub_rb_cmd cmd;

	uint8_t ways, i;

	int j;

	bool stereo_in_use = false;

	bool mall_ss_unsupported = false;

	struct dc_plane_state *plane = NULL;



	if (!dc->ctx->dmub_srv)
@@ -400,22 +400,23 @@ bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable) 
			 */

			ways = dcn32_calculate_cab_allocation(dc, dc->current_state);



			/* MALL not supported with Stereo3D. If any plane is using stereo,

			 * don't try to enter MALL.

			/* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,

			 * or TMZ surface, don't try to enter MALL.

			 */

			for (i = 0; i < dc->current_state->stream_count; i++) {

				for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {

					plane = dc->current_state->stream_status[i].plane_states[j];



					if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO) {

						stereo_in_use = true;

					if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||

							plane->address.tmz_surface) {

						mall_ss_unsupported = true;

						break;

					}

				}

				if (stereo_in_use)

				if (mall_ss_unsupported)

					break;

			}

			if (ways <= dc->caps.cache_num_ways && !stereo_in_use) {

			if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {

				memset(&cmd, 0, sizeof(cmd));

				cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;

				cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
@@ -773,7 +774,8 @@ void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context) 
				hubp->funcs->hubp_update_mall_sel(hubp,

					num_ways <= dc->caps.cache_num_ways &&

					pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&

					pipe->plane_state->address.type !=  PLN_ADDR_TYPE_GRPH_STEREO ? 2 : 0,

					pipe->plane_state->address.type !=  PLN_ADDR_TYPE_GRPH_STEREO &&

					!pipe->plane_state->address.tmz_surface ? 2 : 0,

							cache_cursor);

			}

		}

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+2 −1
Original line number Diff line number Diff line
@@ -674,9 +674,10 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc, 
		 * - Not able to switch in vactive naturally (switching in active means the

		 *   DET provides enough buffer to hide the P-State switch latency -- trying

		 *   to combine this with SubVP can cause issues with the scheduling).

		 * - Not TMZ surface

		 */

		if (pipe->plane_state && !pipe->top_pipe &&

				pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 &&

				pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 && !pipe->plane_state->address.tmz_surface &&

				vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) {

			while (pipe) {

				num_pipes++;