Commit a6098129 authored by Yevgeny Kliteynik's avatar Yevgeny Kliteynik Committed by Saeed Mahameed
Browse files

net/mlx5: DR, Add STEv1 setters and getters 



Add HW specific setter and getters to STEv1 file.
Since STEv0 and STEv1 format are different, each version
should implemented different setters and getters.

Signed-off-by: default avatarAlex Vesker <valex@nvidia.com>
Signed-off-by: default avatarYevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent 9f125ced

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c

+76 −0
Original line number Diff line number Diff line
@@ -55,6 +55,72 @@ enum { 
	DR_STE_V1_LU_TYPE_DONT_CARE			= MLX5DR_STE_LU_TYPE_DONT_CARE,

};



static void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr)

{

	u64 index = miss_addr >> 6;



	MLX5_SET(ste_match_bwc_v1, hw_ste_p, miss_address_39_32, index >> 26);

	MLX5_SET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6, index);

}



static u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p)

{

	u64 index =

		(MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6) |

		 MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_39_32) << 26);



	return index << 6;

}



static void dr_ste_v1_set_byte_mask(u8 *hw_ste_p, u16 byte_mask)

{

	MLX5_SET(ste_match_bwc_v1, hw_ste_p, byte_mask, byte_mask);

}



static u16 dr_ste_v1_get_byte_mask(u8 *hw_ste_p)

{

	return MLX5_GET(ste_match_bwc_v1, hw_ste_p, byte_mask);

}



static void dr_ste_v1_set_lu_type(u8 *hw_ste_p, u16 lu_type)

{

	MLX5_SET(ste_match_bwc_v1, hw_ste_p, entry_format, lu_type >> 8);

	MLX5_SET(ste_match_bwc_v1, hw_ste_p, match_definer_ctx_idx, lu_type & 0xFF);

}



static void dr_ste_v1_set_next_lu_type(u8 *hw_ste_p, u16 lu_type)

{

	MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_entry_format, lu_type >> 8);

	MLX5_SET(ste_match_bwc_v1, hw_ste_p, hash_definer_ctx_idx, lu_type & 0xFF);

}



static u16 dr_ste_v1_get_next_lu_type(u8 *hw_ste_p)

{

	u8 mode = MLX5_GET(ste_match_bwc_v1, hw_ste_p, next_entry_format);

	u8 index = MLX5_GET(ste_match_bwc_v1, hw_ste_p, hash_definer_ctx_idx);



	return (mode << 8 | index);

}



static void dr_ste_v1_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size)

{

	u64 index = (icm_addr >> 5) | ht_size;



	MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_table_base_39_32_size, index >> 27);

	MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_table_base_31_5_size, index);

}



static void dr_ste_v1_init(u8 *hw_ste_p, u16 lu_type,

			   u8 entry_type, u16 gvmi)

{

	dr_ste_v1_set_lu_type(hw_ste_p, lu_type);

	dr_ste_v1_set_next_lu_type(hw_ste_p, MLX5DR_STE_LU_TYPE_DONT_CARE);



	MLX5_SET(ste_match_bwc_v1, hw_ste_p, gvmi, gvmi);

	MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_table_base_63_48, gvmi);

	MLX5_SET(ste_match_bwc_v1, hw_ste_p, miss_address_63_48, gvmi);

}



static void dr_ste_v1_build_eth_l2_src_dst_bit_mask(struct mlx5dr_match_param *value,

						    bool inner, u8 *bit_mask)

{
@@ -885,6 +951,7 @@ static void dr_ste_v1_build_src_gvmi_qpn_init(struct mlx5dr_ste_build *sb, 
}



struct mlx5dr_ste_ctx ste_ctx_v1 = {

	/* Builders */

	.build_eth_l2_src_dst_init	= &dr_ste_v1_build_eth_l2_src_dst_init,

	.build_eth_l3_ipv6_src_init	= &dr_ste_v1_build_eth_l3_ipv6_src_init,

	.build_eth_l3_ipv6_dst_init	= &dr_ste_v1_build_eth_l3_ipv6_dst_init,
@@ -905,4 +972,13 @@ struct mlx5dr_ste_ctx ste_ctx_v1 = { 
	.build_register_0_init		= &dr_ste_v1_build_register_0_init,

	.build_register_1_init		= &dr_ste_v1_build_register_1_init,

	.build_src_gvmi_qpn_init	= &dr_ste_v1_build_src_gvmi_qpn_init,

	/* Getters and Setters */

	.ste_init			= &dr_ste_v1_init,

	.set_next_lu_type		= &dr_ste_v1_set_next_lu_type,

	.get_next_lu_type		= &dr_ste_v1_get_next_lu_type,

	.set_miss_addr			= &dr_ste_v1_set_miss_addr,

	.get_miss_addr			= &dr_ste_v1_get_miss_addr,

	.set_hit_addr			= &dr_ste_v1_set_hit_addr,

	.set_byte_mask			= &dr_ste_v1_set_byte_mask,

	.get_byte_mask			= &dr_ste_v1_get_byte_mask,

};

drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h

+57 −0
Original line number Diff line number Diff line
@@ -4,6 +4,63 @@ 
#ifndef MLX5_IFC_DR_STE_V1_H

#define MLX5_IFC_DR_STE_V1_H



struct mlx5_ifc_ste_match_bwc_v1_bits {

	u8         entry_format[0x8];

	u8         counter_id[0x18];



	u8         miss_address_63_48[0x10];

	u8         match_definer_ctx_idx[0x8];

	u8         miss_address_39_32[0x8];



	u8         miss_address_31_6[0x1a];

	u8         reserved_at_5a[0x1];

	u8         match_polarity[0x1];

	u8         reparse[0x1];

	u8         reserved_at_5d[0x3];



	u8         next_table_base_63_48[0x10];

	u8         hash_definer_ctx_idx[0x8];

	u8         next_table_base_39_32_size[0x8];



	u8         next_table_base_31_5_size[0x1b];

	u8         hash_type[0x2];

	u8         hash_after_actions[0x1];

	u8         reserved_at_9e[0x2];



	u8         byte_mask[0x10];

	u8         next_entry_format[0x1];

	u8         mask_mode[0x1];

	u8         gvmi[0xe];



	u8         action[0x40];

};



struct mlx5_ifc_ste_mask_and_match_v1_bits {

	u8         entry_format[0x8];

	u8         counter_id[0x18];



	u8         miss_address_63_48[0x10];

	u8         match_definer_ctx_idx[0x8];

	u8         miss_address_39_32[0x8];



	u8         miss_address_31_6[0x1a];

	u8         reserved_at_5a[0x1];

	u8         match_polarity[0x1];

	u8         reparse[0x1];

	u8         reserved_at_5d[0x3];



	u8         next_table_base_63_48[0x10];

	u8         hash_definer_ctx_idx[0x8];

	u8         next_table_base_39_32_size[0x8];



	u8         next_table_base_31_5_size[0x1b];

	u8         hash_type[0x2];

	u8         hash_after_actions[0x1];

	u8         reserved_at_9e[0x2];



	u8         action[0x60];

};



struct mlx5_ifc_ste_eth_l2_src_v1_bits {

	u8         reserved_at_0[0x1];

	u8         sx_sniffer[0x1];