Commit a5f7bf54 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Chen-Yu Tsai
Browse files

clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes 



The MFG_BG3D is a gate to enable/disable clock output to the GPU,
but the actual output is decided by multiple muxes; in particular:
mfg_ck_fast_ref muxes between "slow" (top_mfg_core_tmp) and
"fast" (MFGPLL) clock, while top_mfg_core_tmp muxes between the
26MHz clock and various system PLLs.

The clock gate comes after all the muxes, so its parent is
mfg_ck_fast_reg, not top_mfg_core_tmp.
Reparent MFG_BG3D to the latter to match the hardware and add the
CLK_SET_RATE_PARENT flag to it: this way we ensure propagating
rate changes that are requested on MFG_BG3D along its entire clock
tree.

Fixes: 35016f10 ("clk: mediatek: Add MT8195 mfgcfg clock support")
Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-6-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarChen-Yu Tsai <wenst@chromium.org>
parent ae333e63

drivers/clk/mediatek/clk-mt8195-mfg.c

+4 −2
Original line number Diff line number Diff line
@@ -17,10 +17,12 @@ static const struct mtk_gate_regs mfg_cg_regs = { 
};



#define GATE_MFG(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)

	GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs,	\

		       _shift, &mtk_clk_gate_ops_setclr,	\

		       CLK_SET_RATE_PARENT)



static const struct mtk_gate mfg_clks[] = {

	GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "top_mfg_core_tmp", 0),

	GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_ck_fast_ref", 0),

};



static const struct mtk_clk_desc mfg_desc = {