Commit a5e5ceae authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Mauro Carvalho Chehab
Browse files

media: atomisp: Move MIPI_PORT_LANES to the only user 

Move MIPI_PORT_LANES to the only user of it, i.e. pci/runtime/isys/src/rx.c.

Link: https://lore.kernel.org/linux-media/20210713152523.19902-4-andriy.shevchenko@linux.intel.com


Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 69aa1dee

drivers/staging/media/atomisp/pci/isp2400_input_system_local.h

+0 −11
Original line number Diff line number Diff line
@@ -362,17 +362,6 @@ static const hrt_address __maybe_unused MIPI_PORT_OFFSET[N_MIPI_PORT_ID] = { 
	0x00000200UL

};



static const mipi_lane_cfg_t MIPI_PORT_LANES[N_RX_MODE][N_MIPI_PORT_ID] = {

	{MIPI_4LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG},

	{MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG},

	{MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG},

	{MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG},

	{MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_2LANE_CFG},

	{MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG},

	{MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG},

	{MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}

};



static const hrt_address __maybe_unused SUB_SYSTEM_OFFSET[N_SUB_SYSTEM_ID] = {

	0x00001000UL,

	0x00002000UL,

drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c

+11 −0
Original line number Diff line number Diff line
@@ -476,6 +476,17 @@ unsigned int ia_css_csi2_calculate_input_system_alignment( 
#endif



#if !defined(ISP2401)

static const mipi_lane_cfg_t MIPI_PORT_LANES[N_RX_MODE][N_MIPI_PORT_ID] = {

	{MIPI_4LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG},

	{MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG},

	{MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG},

	{MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG},

	{MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_2LANE_CFG},

	{MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG},

	{MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG},

	{MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}

};



void ia_css_isys_rx_configure(const rx_cfg_t *config,

			      const enum ia_css_input_mode input_mode)

{