dt-bindings: usb: dwc3-xilinx: Convert USB DWC3 bindings

Xilinx SuperSpeed DWC3 USB SoC controller

Required properties:

- compatible:	May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"

- reg:		Base address and length of the register control block

- clocks:	A list of phandles for the clocks listed in clock-names

- clock-names:	Should contain the following:

  "bus_clk"	 Master/Core clock, have to be >= 125 MHz for SS

		 operation and >= 60MHz for HS operation

  "ref_clk"	 Clock source to core during PHY power down

- resets:	A list of phandles for resets listed in reset-names

- reset-names:

  "usb_crst"	 USB core reset

  "usb_hibrst"	 USB hibernation reset

  "usb_apbrst"	 USB APB reset

Required child node:

A child node must exist to represent the core DWC3 IP block. The name of

the node is not important. The content of the node is defined in dwc3.txt.

Optional properties for snps,dwc3:

- dma-coherent:	Enable this flag if CCI is enabled in design. Adding this

		flag configures Global SoC bus Configuration Register and

		Xilinx USB 3.0 IP - USB coherency register to enable CCI.

- interrupt-names: Should contain the following:

  "dwc_usb3"	USB gadget mode interrupts

  "otg"		USB OTG mode interrupts

  "hiber"	USB hibernation interrupts

Example device node:

		usb@0 {

			#address-cells = <0x2>;

			#size-cells = <0x1>;

			compatible = "xlnx,zynqmp-dwc3";

			reg = <0x0 0xff9d0000 0x0 0x100>;

			clock-names = "bus_clk", "ref_clk";

			clocks = <&clk125>, <&clk125>;

			resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,

				 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,

				 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;

			reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";

			ranges;

			dwc3@fe200000 {

				compatible = "snps,dwc3";

				reg = <0x0 0xfe200000 0x40000>;

				interrupt-names = "dwc_usb3", "otg", "hiber";

				interrupts = <0 65 4>, <0 69 4>, <0 75 4>;

				phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;

				phy-names = "usb3-phy";

				dr_mode = "host";

				dma-coherent;

			};

		};

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx SuperSpeed DWC3 USB SoC controller

maintainers:

  - Manish Narani <manish.narani@xilinx.com>

properties:

  compatible:

    items:

      - enum:

          - xlnx,zynqmp-dwc3

          - xlnx,versal-dwc3

  reg:

    maxItems: 1

  "#address-cells":

    enum: [ 1, 2 ]

  "#size-cells":

    enum: [ 1, 2 ]

  ranges: true

  power-domains:

    description: specifies a phandle to PM domain provider node

    maxItems: 1

  clocks:

    description:

      A list of phandle and clock-specifier pairs for the clocks

      listed in clock-names.

    items:

      - description: Master/Core clock, has to be >= 125 MHz

          for SS operation and >= 60MHz for HS operation.

      - description: Clock source to core during PHY power down.

  clock-names:

    items:

      - const: bus_clk

      - const: ref_clk

  resets:

    description:

      A list of phandles for resets listed in reset-names.

    items:

      - description: USB core reset

      - description: USB hibernation reset

      - description: USB APB reset

  reset-names:

    items:

      - const: usb_crst

      - const: usb_hibrst

      - const: usb_apbrst

  phys:

    minItems: 1

    maxItems: 2

  phy-names:

    minItems: 1

    maxItems: 2

    items:

      enum:

        - usb2-phy

        - usb3-phy

# Required child node:

patternProperties:

  "^usb@[0-9a-f]+$":

    $ref: snps,dwc3.yaml#

required:

  - compatible

  - reg

  - "#address-cells"

  - "#size-cells"

  - ranges

  - power-domains

  - clocks

  - clock-names

  - resets

  - reset-names

additionalProperties: false

examples:

  - |

    #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>

    #include <dt-bindings/power/xlnx-zynqmp-power.h>

    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>

    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>

    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>

    #include <dt-bindings/phy/phy.h>

    axi {

        #address-cells = <2>;

        #size-cells = <2>;

        usb@0 {

            #address-cells = <0x2>;

            #size-cells = <0x2>;

            compatible = "xlnx,zynqmp-dwc3";

            reg = <0x0 0xff9d0000 0x0 0x100>;

            clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;

            clock-names = "bus_clk", "ref_clk";

            power-domains = <&zynqmp_firmware PD_USB_0>;

            resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,

                     <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,

                     <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;

            reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";

            phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;

            phy-names = "usb3-phy";

            ranges;

            usb@fe200000 {

                compatible = "snps,dwc3";

                reg = <0x0 0xfe200000 0x0 0x40000>;

                interrupt-names = "host", "otg";

                interrupts = <0 65 4>, <0 69 4>;

                dr_mode = "host";

                dma-coherent;

            };

        };

    };