Commit a56ab7c7 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/nohash: Convert set_context() to C 



ppc8xx already has set_context() in C.

Other ones have it in assembly. The only thing it does is to
write the context id into SPRN_PID.

Do it in C.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/a5d0759064f3831c6b88af49ef5d3b05ba1c4dad.1622712515.git.christophe.leroy@csgroup.eu
parent 25910260

arch/powerpc/include/asm/mmu_context.h

+0 −1
Original line number Diff line number Diff line
@@ -57,7 +57,6 @@ static inline bool mm_iommu_is_devmem(struct mm_struct *mm, unsigned long hpa, 
static inline void mm_iommu_init(struct mm_struct *mm) { }

#endif

extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);

extern void set_context(unsigned long id, pgd_t *pgd);



#ifdef CONFIG_PPC_BOOK3S_64

extern void radix__switch_mmu_context(struct mm_struct *prev,

arch/powerpc/kernel/head_40x.S

+0 −7
Original line number Diff line number Diff line
@@ -702,13 +702,6 @@ _GLOBAL(abort) 
        oris    r13,r13,DBCR0_RST_SYSTEM@h

        mtspr   SPRN_DBCR0,r13



_GLOBAL(set_context)

	sync

	mtspr	SPRN_PID,r3

	isync				/* Need an isync to flush shadow */

					/* TLBs after changing PID */

	blr



/* We put a few things here that have to be page-aligned. This stuff

 * goes at the beginning of the data segment, which is page-aligned.

 */

arch/powerpc/kernel/head_44x.S

+0 −5
Original line number Diff line number Diff line
@@ -788,11 +788,6 @@ _GLOBAL(__fixup_440A_mcheck) 
	sync

	blr



_GLOBAL(set_context)

	mtspr	SPRN_PID,r3

	isync			/* Force context change */

	blr



/*

 * Init CPU state. This is called at boot time or for secondary CPUs

 * to setup initial TLB entries, setup IVORs, etc...

arch/powerpc/kernel/head_fsl_booke.S

+0 −5
Original line number Diff line number Diff line
@@ -985,11 +985,6 @@ _GLOBAL(abort) 
	mtspr	SPRN_DBCR0,r13

	isync



_GLOBAL(set_context)

	mtspr	SPRN_PID,r3

	isync			/* Force context change */

	blr



#ifdef CONFIG_SMP

/* When we get here, r24 needs to hold the CPU # */

	.globl __secondary_start

arch/powerpc/mm/nohash/8xx.c

+0 −25
Original line number Diff line number Diff line
@@ -212,31 +212,6 @@ void __init setup_initial_memory_limit(phys_addr_t first_memblock_base, 
	memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_32M));

}



/*

 * Set up to use a given MMU context.

 * id is context number, pgd is PGD pointer.

 *

 * We place the physical address of the new task page directory loaded

 * into the MMU base register, and set the ASID compare register with

 * the new "context."

 */

void set_context(unsigned long id, pgd_t *pgd)

{

	s16 offset = (s16)(__pa(swapper_pg_dir));



	/* Register M_TWB will contain base address of level 1 table minus the

	 * lower part of the kernel PGDIR base address, so that all accesses to

	 * level 1 table are done relative to lower part of kernel PGDIR base

	 * address.

	 */

	mtspr(SPRN_M_TWB, __pa(pgd) - offset);



	/* Update context */

	mtspr(SPRN_M_CASID, id - 1);

	/* sync */

	mb();

}



#ifdef CONFIG_PPC_KUEP

void __init setup_kuep(bool disabled)

{