Commit a54c61f4 authored by Michael Ellerman's avatar Michael Ellerman
Browse files

Merge branch 'fixes' into next 

We have some dependencies & conflicts between patches in fixes and
things to go in next, both in the radix TLB flush code and the IMC PMU
driver. So merge fixes into next.
parents 77fad8bf 7ecb37f6

arch/powerpc/include/asm/code-patching.h

+1 −9
Original line number Diff line number Diff line
@@ -83,15 +83,7 @@ static inline unsigned long ppc_function_entry(void *func) 
	 * On PPC64 ABIv1 the function pointer actually points to the

	 * function's descriptor. The first entry in the descriptor is the

	 * address of the function text.

	 *

	 * However, we may also receive pointer to an assembly symbol. To

	 * detect that, we first check if the function pointer we receive

	 * already points to kernel/module text and we only dereference it

	 * if it doesn't.

	 */

	if (kernel_text_address((unsigned long)func))

		return (unsigned long)func;

	else

	return ((func_descr_t *)func)->entry;

#else

	return (unsigned long)func;

arch/powerpc/kernel/align.c

+1 −1
Original line number Diff line number Diff line
@@ -332,7 +332,7 @@ int fix_alignment(struct pt_regs *regs) 
	 * when pasting to a co-processor. Furthermore, paste_last is the

	 * synchronisation point for preceding copy/paste sequences.

	 */

	if ((instr & 0xfc0006fe) == PPC_INST_COPY)

	if ((instr & 0xfc0006fe) == (PPC_INST_COPY & 0xfc0006fe))

		return -EIO;



	r = analyse_instr(&op, regs, instr);

arch/powerpc/kernel/dt_cpu_ftrs.c

+2 −2
Original line number Diff line number Diff line
@@ -102,10 +102,10 @@ static void cpufeatures_flush_tlb(void) 
	case PVR_POWER8:

	case PVR_POWER8E:

	case PVR_POWER8NVL:

		__flush_tlb_power8(POWER8_TLB_SETS);

		__flush_tlb_power8(TLB_INVAL_SCOPE_GLOBAL);

		break;

	case PVR_POWER9:

		__flush_tlb_power9(POWER9_TLB_SETS_HASH);

		__flush_tlb_power9(TLB_INVAL_SCOPE_GLOBAL);

		break;

	default:

		pr_err("unknown CPU version for boot TLB flush\n");

arch/powerpc/kernel/kprobes.c

+6 −1
Original line number Diff line number Diff line
@@ -605,7 +605,12 @@ NOKPROBE_SYMBOL(kprobe_fault_handler); 


unsigned long arch_deref_entry_point(void *entry)

{

#ifdef PPC64_ELF_ABI_v1

	if (!kernel_text_address((unsigned long)entry))

		return ppc_global_function_entry(entry);

	else

#endif

		return (unsigned long)entry;

}

NOKPROBE_SYMBOL(arch_deref_entry_point);

arch/powerpc/kernel/mce_power.c

+13 −0
Original line number Diff line number Diff line
@@ -717,5 +717,18 @@ long __machine_check_early_realmode_p8(struct pt_regs *regs) 


long __machine_check_early_realmode_p9(struct pt_regs *regs)

{

	/*

	 * On POWER9 DD2.1 and below, it's possible to get a machine check

	 * caused by a paste instruction where only DSISR bit 25 is set. This

	 * will result in the MCE handler seeing an unknown event and the kernel

	 * crashing. An MCE that occurs like this is spurious, so we don't need

	 * to do anything in terms of servicing it. If there is something that

	 * needs to be serviced, the CPU will raise the MCE again with the

	 * correct DSISR so that it can be serviced properly. So detect this

	 * case and mark it as handled.

	 */

	if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000)

		return 1;



	return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table);

}