Commit a51969fa authored by Jeffrey Hugo's avatar Jeffrey Hugo Committed by Kishon Vijay Abraham I
Browse files

phy: qcom-qmp: Add QMP V3 USB3 PHY support for msm8998 



MSM8998 contains a single QMP v3 USB3 phy similar to the existing sdm845
support.

Signed-off-by: default avatarJeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent 0ade2930

drivers/phy/qualcomm/phy-qcom-qmp.c

+140 −0
Original line number Diff line number Diff line
@@ -687,6 +687,116 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),

};



static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),

};



static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),

};



static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),

};



static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),

};





/* struct qmp_phy_cfg - per-PHY initialization config */

struct qmp_phy_cfg {

	/* phy-type - PCIE/UFS/USB */
@@ -1036,6 +1146,33 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { 
	.no_pcs_sw_reset	= true,

};



static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {

	.type                   = PHY_TYPE_USB3,

	.nlanes                 = 1,



	.serdes_tbl             = msm8998_usb3_serdes_tbl,

	.serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),

	.tx_tbl                 = msm8998_usb3_tx_tbl,

	.tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),

	.rx_tbl                 = msm8998_usb3_rx_tbl,

	.rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),

	.pcs_tbl                = msm8998_usb3_pcs_tbl,

	.pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),

	.clk_list               = msm8996_phy_clk_l,

	.num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),

	.reset_list             = msm8996_usb3phy_reset_l,

	.num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),

	.vreg_list              = qmp_phy_vreg_l,

	.num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),

	.regs                   = qmp_v3_usb3phy_regs_layout,



	.start_ctrl             = SERDES_START | PCS_START,

	.pwrdn_ctrl             = SW_PWRDN,

	.mask_pcs_ready         = PHYSTATUS,



	.is_dual_lane_phy       = true,

};



static void qcom_qmp_phy_configure(void __iomem *base,

				   const unsigned int *regs,

				   const struct qmp_phy_init_tbl tbl[],
@@ -1747,6 +1884,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { 
	}, {

		.compatible = "qcom,sdm845-qmp-ufs-phy",

		.data = &sdm845_ufsphy_cfg,

	}, {

		.compatible = "qcom,msm8998-qmp-usb3-phy",

		.data = &msm8998_usb3phy_cfg,

	},

	{ },

};

drivers/phy/qualcomm/phy-qcom-qmp.h

+4 −0
Original line number Diff line number Diff line
@@ -174,6 +174,7 @@ 
#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1		0x0c4

#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1		0x0c8

#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1		0x0cc

#define QSERDES_V3_COM_INTEGLOOP_INITVAL		0x0d0

#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0		0x0d8

#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0		0x0dc

#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1		0x0e0
@@ -201,6 +202,7 @@ 
#define QSERDES_V3_COM_DEBUG_BUS2			0x170

#define QSERDES_V3_COM_DEBUG_BUS3			0x174

#define QSERDES_V3_COM_DEBUG_BUS_SEL			0x178

#define QSERDES_V3_COM_CMN_MODE				0x184



/* Only for QMP V3 PHY - TX registers */

#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX		0x044
@@ -211,6 +213,7 @@ 
#define QSERDES_V3_TX_RCV_DETECT_LVL_2			0x0a4



/* Only for QMP V3 PHY - RX registers */

#define QSERDES_V3_RX_UCDR_FO_GAIN			0x008

#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF			0x00c

#define QSERDES_V3_RX_UCDR_SO_GAIN			0x014

#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF		0x024
@@ -219,6 +222,7 @@ 
#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN		0x030

#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034

#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c

#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH		0x040

#define QSERDES_V3_RX_UCDR_PI_CONTROLS			0x044

#define QSERDES_V3_RX_RX_TERM_BW			0x07c

#define QSERDES_V3_RX_VGA_CAL_CNTRL1			0x0bc