Commit a5043ed9 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update ICL events to v1.13 

Events are generated for Icelake v1.13 with events from:

  https://download.01.org/perfmon/ICL/

Using the scripts at:

  https://github.com/intel/event-converter-for-linux-perf/



This change updates descriptions and adds INST_DECODED.DECODERS.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220428075730.797727-2-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 44900ce9

tools/perf/pmu-events/arch/x86/icelake/cache.json

+1 −40
Original line number Diff line number Diff line
@@ -563,7 +563,6 @@ 
        "MSRValue": "0x3FC03C0004",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -578,7 +577,6 @@ 
        "MSRValue": "0x10003C0004",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -593,7 +591,6 @@ 
        "MSRValue": "0x4003C0004",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -608,7 +605,6 @@ 
        "MSRValue": "0x2003C0004",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -623,7 +619,6 @@ 
        "MSRValue": "0x1003C0004",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -638,7 +633,6 @@ 
        "MSRValue": "0x1E003C0004",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -653,7 +647,6 @@ 
        "MSRValue": "0x3FC03C0001",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -668,7 +661,6 @@ 
        "MSRValue": "0x10003C0001",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -683,7 +675,6 @@ 
        "MSRValue": "0x4003C0001",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -698,7 +689,6 @@ 
        "MSRValue": "0x2003C0001",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -713,7 +703,6 @@ 
        "MSRValue": "0x1003C0001",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -728,7 +717,6 @@ 
        "MSRValue": "0x1E003C0001",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -743,7 +731,6 @@ 
        "MSRValue": "0x3FC03C0002",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -758,7 +745,6 @@ 
        "MSRValue": "0x10003C0002",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -773,7 +759,6 @@ 
        "MSRValue": "0x4003C0002",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -788,7 +773,6 @@ 
        "MSRValue": "0x2003C0002",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -803,7 +787,6 @@ 
        "MSRValue": "0x1003C0002",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -818,7 +801,6 @@ 
        "MSRValue": "0x1E003C0002",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -833,7 +815,6 @@ 
        "MSRValue": "0x3FC03C0400",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -848,7 +829,6 @@ 
        "MSRValue": "0x2003C0400",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -863,7 +843,6 @@ 
        "MSRValue": "0x1003C0400",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -878,7 +857,6 @@ 
        "MSRValue": "0x3FC03C0010",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -893,7 +871,6 @@ 
        "MSRValue": "0x10003C0010",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -908,7 +885,6 @@ 
        "MSRValue": "0x4003C0010",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -923,7 +899,6 @@ 
        "MSRValue": "0x2003C0010",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -938,7 +913,6 @@ 
        "MSRValue": "0x1003C0010",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -953,7 +927,6 @@ 
        "MSRValue": "0x1E003C0010",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -968,7 +941,6 @@ 
        "MSRValue": "0x3FC03C0020",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -983,7 +955,6 @@ 
        "MSRValue": "0x10003C0020",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -998,7 +969,6 @@ 
        "MSRValue": "0x4003C0020",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -1013,7 +983,6 @@ 
        "MSRValue": "0x2003C0020",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -1028,7 +997,6 @@ 
        "MSRValue": "0x1003C0020",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -1043,7 +1011,6 @@ 
        "MSRValue": "0x1E003C0020",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -1058,7 +1025,6 @@ 
        "MSRValue": "0x3FC03C2380",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -1073,7 +1039,6 @@ 
        "MSRValue": "0x4003C8000",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -1088,7 +1053,6 @@ 
        "MSRValue": "0x2003C8000",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -1103,7 +1067,6 @@ 
        "MSRValue": "0x1003C8000",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -1118,7 +1081,6 @@ 
        "MSRValue": "0x1E003C8000",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -1133,7 +1095,6 @@ 
        "MSRValue": "0x3FC03C0800",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"

tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json

+0 −12
Original line number Diff line number Diff line
@@ -17,18 +17,6 @@ 
        "MetricGroup": "Ret;Summary",

        "MetricName": "IPC"

    },

    {

        "BriefDescription": "Uops Per Instruction",

        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",

        "MetricGroup": "Pipeline;Ret;Retire",

        "MetricName": "UPI"

    },

    {

        "BriefDescription": "Instruction per taken branch",

        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",

        "MetricGroup": "Branches;Fed;FetchBW",

        "MetricName": "UpTB"

    },

    {

        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",

        "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)",

tools/perf/pmu-events/arch/x86/icelake/memory.json

+1 −9
Original line number Diff line number Diff line
@@ -239,7 +239,6 @@ 
        "MSRValue": "0x3FFFC00004",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -254,7 +253,6 @@ 
        "MSRValue": "0x3FFFC00001",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -269,7 +267,6 @@ 
        "MSRValue": "0x3FFFC00002",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -284,7 +281,6 @@ 
        "MSRValue": "0x3FFFC00400",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -299,7 +295,6 @@ 
        "MSRValue": "0x3FFFC00010",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -314,7 +309,6 @@ 
        "MSRValue": "0x3FFFC00020",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -329,7 +323,6 @@ 
        "MSRValue": "0x3FFFC08000",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"
@@ -344,7 +337,6 @@ 
        "MSRValue": "0x3FFFC00800",

        "Offcore": "1",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"

tools/perf/pmu-events/arch/x86/icelake/other.json

+0 −24

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/icelake/pipeline.json

+12 −0
Original line number Diff line number Diff line
@@ -452,6 +452,18 @@ 
        "Speculative": "1",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Instruction decoders utilized in a cycle",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x55",

        "EventName": "INST_DECODED.DECODERS",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",

        "CollectPEBSRecord": "2",