Commit a4a49140 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/smccc' into for-next/core 

Add support for versions v1.2 and 1.3 of the SMC calling convention.

* for-next/smccc:
  arm64: smccc: Support SMCCC v1.3 SVE register saving hint
  arm64: smccc: Add support for SMCCCv1.2 extended input/output registers
parents 26a0f50f cfa7ff95

arch/arm64/kernel/asm-offsets.c

+9 −0
Original line number Diff line number Diff line
@@ -140,6 +140,15 @@ int main(void) 
  DEFINE(ARM_SMCCC_RES_X2_OFFS,		offsetof(struct arm_smccc_res, a2));

  DEFINE(ARM_SMCCC_QUIRK_ID_OFFS,	offsetof(struct arm_smccc_quirk, id));

  DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS,	offsetof(struct arm_smccc_quirk, state));

  DEFINE(ARM_SMCCC_1_2_REGS_X0_OFFS,	offsetof(struct arm_smccc_1_2_regs, a0));

  DEFINE(ARM_SMCCC_1_2_REGS_X2_OFFS,	offsetof(struct arm_smccc_1_2_regs, a2));

  DEFINE(ARM_SMCCC_1_2_REGS_X4_OFFS,	offsetof(struct arm_smccc_1_2_regs, a4));

  DEFINE(ARM_SMCCC_1_2_REGS_X6_OFFS,	offsetof(struct arm_smccc_1_2_regs, a6));

  DEFINE(ARM_SMCCC_1_2_REGS_X8_OFFS,	offsetof(struct arm_smccc_1_2_regs, a8));

  DEFINE(ARM_SMCCC_1_2_REGS_X10_OFFS,	offsetof(struct arm_smccc_1_2_regs, a10));

  DEFINE(ARM_SMCCC_1_2_REGS_X12_OFFS,	offsetof(struct arm_smccc_1_2_regs, a12));

  DEFINE(ARM_SMCCC_1_2_REGS_X14_OFFS,	offsetof(struct arm_smccc_1_2_regs, a14));

  DEFINE(ARM_SMCCC_1_2_REGS_X16_OFFS,	offsetof(struct arm_smccc_1_2_regs, a16));

  BLANK();

  DEFINE(HIBERN_PBE_ORIG,	offsetof(struct pbe, orig_address));

  DEFINE(HIBERN_PBE_ADDR,	offsetof(struct pbe, address));

arch/arm64/kernel/smccc-call.S

+83 −0
Original line number Diff line number Diff line
@@ -7,8 +7,34 @@ 


#include <asm/asm-offsets.h>

#include <asm/assembler.h>

#include <asm/thread_info.h>



/*

 * If we have SMCCC v1.3 and (as is likely) no SVE state in

 * the registers then set the SMCCC hint bit to say there's no

 * need to preserve it.  Do this by directly adjusting the SMCCC

 * function value which is already stored in x0 ready to be called.

 */

SYM_FUNC_START(__arm_smccc_sve_check)



	ldr_l	x16, smccc_has_sve_hint

	cbz	x16, 2f



	get_current_task x16

	ldr	x16, [x16, #TSK_TI_FLAGS]

	tbnz	x16, #TIF_FOREIGN_FPSTATE, 1f	// Any live FP state?

	tbnz	x16, #TIF_SVE, 2f		// Does that state include SVE?



1:	orr	x0, x0, ARM_SMCCC_1_3_SVE_HINT



2:	ret

SYM_FUNC_END(__arm_smccc_sve_check)

EXPORT_SYMBOL(__arm_smccc_sve_check)



	.macro SMCCC instr

alternative_if ARM64_SVE

	bl	__arm_smccc_sve_check

alternative_else_nop_endif

	\instr	#0

	ldr	x4, [sp]

	stp	x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
@@ -43,3 +69,60 @@ SYM_FUNC_START(__arm_smccc_hvc) 
	SMCCC	hvc

SYM_FUNC_END(__arm_smccc_hvc)

EXPORT_SYMBOL(__arm_smccc_hvc)



	.macro SMCCC_1_2 instr

	/* Save `res` and free a GPR that won't be clobbered */

	stp     x1, x19, [sp, #-16]!



	/* Ensure `args` won't be clobbered while loading regs in next step */

	mov	x19, x0



	/* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */

	ldp	x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]

	ldp	x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]

	ldp	x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]

	ldp	x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]

	ldp	x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]

	ldp	x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]

	ldp	x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]

	ldp	x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]

	ldp	x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]



	\instr #0



	/* Load the `res` from the stack */

	ldr	x19, [sp]



	/* Store the registers x0 - x17 into the result structure */

	stp	x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]

	stp	x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]

	stp	x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]

	stp	x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]

	stp	x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]

	stp	x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]

	stp	x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]

	stp	x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]

	stp	x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]



	/* Restore original x19 */

	ldp     xzr, x19, [sp], #16

	ret

.endm



/*

 * void arm_smccc_1_2_hvc(const struct arm_smccc_1_2_regs *args,

 *			  struct arm_smccc_1_2_regs *res);

 */

SYM_FUNC_START(arm_smccc_1_2_hvc)

	SMCCC_1_2 hvc

SYM_FUNC_END(arm_smccc_1_2_hvc)

EXPORT_SYMBOL(arm_smccc_1_2_hvc)



/*

 * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,

 *			  struct arm_smccc_1_2_regs *res);

 */

SYM_FUNC_START(arm_smccc_1_2_smc)

	SMCCC_1_2 smc

SYM_FUNC_END(arm_smccc_1_2_smc)

EXPORT_SYMBOL(arm_smccc_1_2_smc)

drivers/firmware/smccc/smccc.c

+4 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ static u32 smccc_version = ARM_SMCCC_VERSION_1_0; 
static enum arm_smccc_conduit smccc_conduit = SMCCC_CONDUIT_NONE;



bool __ro_after_init smccc_trng_available = false;

u64 __ro_after_init smccc_has_sve_hint = false;



void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)

{
@@ -22,6 +23,9 @@ void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit) 
	smccc_conduit = conduit;



	smccc_trng_available = smccc_probe_trng();

	if (IS_ENABLED(CONFIG_ARM64_SVE) &&

	    smccc_version >= ARM_SMCCC_VERSION_1_3)

		smccc_has_sve_hint = true;

}



enum arm_smccc_conduit arm_smccc_1_1_get_conduit(void)

include/linux/arm-smccc.h

+86 −2
Original line number Diff line number Diff line
@@ -63,6 +63,9 @@ 
#define ARM_SMCCC_VERSION_1_0		0x10000

#define ARM_SMCCC_VERSION_1_1		0x10001

#define ARM_SMCCC_VERSION_1_2		0x10002

#define ARM_SMCCC_VERSION_1_3		0x10003



#define ARM_SMCCC_1_3_SVE_HINT		0x10000



#define ARM_SMCCC_VERSION_FUNC_ID					\

	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,				\
@@ -216,6 +219,8 @@ u32 arm_smccc_get_version(void); 


void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit);



extern u64 smccc_has_sve_hint;



/**

 * struct arm_smccc_res - Result from SMC/HVC call

 * @a0-a3 result values from registers 0 to 3
@@ -227,6 +232,61 @@ struct arm_smccc_res { 
	unsigned long a3;

};



#ifdef CONFIG_ARM64

/**

 * struct arm_smccc_1_2_regs - Arguments for or Results from SMC/HVC call

 * @a0-a17 argument values from registers 0 to 17

 */

struct arm_smccc_1_2_regs {

	unsigned long a0;

	unsigned long a1;

	unsigned long a2;

	unsigned long a3;

	unsigned long a4;

	unsigned long a5;

	unsigned long a6;

	unsigned long a7;

	unsigned long a8;

	unsigned long a9;

	unsigned long a10;

	unsigned long a11;

	unsigned long a12;

	unsigned long a13;

	unsigned long a14;

	unsigned long a15;

	unsigned long a16;

	unsigned long a17;

};



/**

 * arm_smccc_1_2_hvc() - make HVC calls

 * @args: arguments passed via struct arm_smccc_1_2_regs

 * @res: result values via struct arm_smccc_1_2_regs

 *

 * This function is used to make HVC calls following SMC Calling Convention

 * v1.2 or above. The content of the supplied param are copied from the

 * structure to registers prior to the HVC instruction. The return values

 * are updated with the content from registers on return from the HVC

 * instruction.

 */

asmlinkage void arm_smccc_1_2_hvc(const struct arm_smccc_1_2_regs *args,

				  struct arm_smccc_1_2_regs *res);



/**

 * arm_smccc_1_2_smc() - make SMC calls

 * @args: arguments passed via struct arm_smccc_1_2_regs

 * @res: result values via struct arm_smccc_1_2_regs

 *

 * This function is used to make SMC calls following SMC Calling Convention

 * v1.2 or above. The content of the supplied param are copied from the

 * structure to registers prior to the SMC instruction. The return values

 * are updated with the content from registers on return from the SMC

 * instruction.

 */

asmlinkage void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,

				  struct arm_smccc_1_2_regs *res);

#endif



/**

 * struct arm_smccc_quirk - Contains quirk information

 * @id: quirk identification
@@ -240,6 +300,15 @@ struct arm_smccc_quirk { 
	} state;

};



/**

 * __arm_smccc_sve_check() - Set the SVE hint bit when doing SMC calls

 *

 * Sets the SMCCC hint bit to indicate if there is live state in the SVE

 * registers, this modifies x0 in place and should never be called from C

 * code.

 */

asmlinkage unsigned long __arm_smccc_sve_check(unsigned long x0);



/**

 * __arm_smccc_smc() - make SMC calls

 * @a0-a7: arguments passed in registers 0 to 7
@@ -297,6 +366,20 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, 


#endif



/* nVHE hypervisor doesn't have a current thread so needs separate checks */

#if defined(CONFIG_ARM64_SVE) && !defined(__KVM_NVHE_HYPERVISOR__)



#define SMCCC_SVE_CHECK ALTERNATIVE("nop \n",  "bl __arm_smccc_sve_check \n", \

				    ARM64_SVE)

#define smccc_sve_clobbers "x16", "x30", "cc",



#else



#define SMCCC_SVE_CHECK

#define smccc_sve_clobbers



#endif



#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x



#define __count_args(...)						\
@@ -364,7 +447,7 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, 


#define ___constraints(count)						\

	: __constraint_read_ ## count					\

	: "memory"

	: smccc_sve_clobbers "memory"

#define __constraints(count)	___constraints(count)



/*
@@ -379,7 +462,8 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, 
		register unsigned long r2 asm("r2");			\

		register unsigned long r3 asm("r3"); 			\

		__declare_args(__count_args(__VA_ARGS__), __VA_ARGS__);	\

		asm volatile(inst "\n" :				\

		asm volatile(SMCCC_SVE_CHECK				\

			     inst "\n" :				\

			     "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)	\

			     __constraints(__count_args(__VA_ARGS__)));	\

		if (___res)						\