Commit a4a0ce24 authored by Dan Williams's avatar Dan Williams
Browse files

tools/testing/cxl: Fix root port to host bridge assignment 

Mocked root-ports are meant to be round-robin assigned to host-bridges.

Fixes: 67dcdd4d ("tools/testing/cxl: Introduce a mocked-up CXL port hierarchy")
Link: https://lore.kernel.org/r/164298431629.3018233.14004377108116384485.stgit@dwillia2-desk3.amr.corp.intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent f246abd6

tools/testing/cxl/test/cxl.c

+1 −1
Original line number Diff line number Diff line
@@ -558,7 +558,7 @@ static __init int cxl_test_init(void) 


	for (i = 0; i < ARRAY_SIZE(cxl_root_port); i++) {

		struct platform_device *bridge =

			cxl_host_bridge[i / NR_CXL_ROOT_PORTS];

			cxl_host_bridge[i % ARRAY_SIZE(cxl_host_bridge)];

		struct platform_device *pdev;



		pdev = platform_device_alloc("cxl_root_port", i);