Commit a4855a8c authored by Srujana Challa's avatar Srujana Challa Committed by Herbert Xu
Browse files

crypto: octeontx2 - hardware configuration for inline IPsec 



On OcteonTX2/OctoenTX3 variants of silicon, Admin function (AF)
handles resource allocation and configuration for PFs and their VFs.
PFs request the AF directly, via mailboxes.
Unlike PFs, VFs cannot send a mailbox request directly. A VF sends
mailbox messages to its parent PF, with which it shares a
mailbox region. The PF then forwards these messages to the AF.

This patch adds code to configure inline-IPsec HW resources for
CPT VFs as CPT VFs cannot send a mailbox request directly to AF.

Signed-off-by: default avatarSrujana Challa <schalla@marvell.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 5c553114

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

+15 −0
Original line number Diff line number Diff line
@@ -40,10 +40,25 @@ enum otx2_cpt_eng_type { 
};



/* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */

#define MBOX_MSG_RX_INLINE_IPSEC_LF_CFG 0xBFE

#define MBOX_MSG_GET_ENG_GRP_NUM        0xBFF

#define MBOX_MSG_GET_CAPS               0xBFD

#define MBOX_MSG_GET_KVF_LIMITS         0xBFC



/*

 * Message request to config cpt lf for inline inbound ipsec.

 * This message is only used between CPT PF <-> CPT VF

 */

struct otx2_cpt_rx_inline_lf_cfg {

	struct mbox_msghdr hdr;

	u16 sso_pf_func;

	u16 param1;

	u16 param2;

	u16 opcode;

	u32 credit;

	u32 reserved;

};



/*

 * Message request and response to get engine group number

 * which has attached a given type of engines (SE, AE, IE)

drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

+3 −0
Original line number Diff line number Diff line
@@ -141,6 +141,8 @@ int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs) 
	req->hdr.sig = OTX2_MBOX_REQ_SIG;

	req->hdr.pcifunc = 0;

	req->cptlfs = lfs->lfs_num;

	req->cpt_blkaddr = lfs->blkaddr;

	req->modify = 1;

	ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);

	if (ret)

		return ret;
@@ -168,6 +170,7 @@ int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs) 
	req->hdr.id = MBOX_MSG_DETACH_RESOURCES;

	req->hdr.sig = OTX2_MBOX_REQ_SIG;

	req->hdr.pcifunc = 0;

	req->cptlfs = 1;

	ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);

	if (ret)

		return ret;

drivers/crypto/marvell/octeontx2/otx2_cptlf.c

+17 −17
Original line number Diff line number Diff line
@@ -13,10 +13,10 @@ static void cptlf_do_set_done_time_wait(struct otx2_cptlf_info *lf, 
{

	union otx2_cptx_lf_done_wait done_wait;



	done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

				      OTX2_CPT_LF_DONE_WAIT);

	done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,

				      lf->slot, OTX2_CPT_LF_DONE_WAIT);

	done_wait.s.time_wait = time_wait;

	otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

	otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

			 OTX2_CPT_LF_DONE_WAIT, done_wait.u);

}
@@ -24,10 +24,10 @@ static void cptlf_do_set_done_num_wait(struct otx2_cptlf_info *lf, int num_wait) 
{

	union otx2_cptx_lf_done_wait done_wait;



	done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

				      OTX2_CPT_LF_DONE_WAIT);

	done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,

				      lf->slot, OTX2_CPT_LF_DONE_WAIT);

	done_wait.s.num_wait = num_wait;

	otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

	otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

			 OTX2_CPT_LF_DONE_WAIT, done_wait.u);

}
@@ -147,7 +147,7 @@ static void cptlf_set_misc_intrs(struct otx2_cptlfs_info *lfs, u8 enable) 
	irq_misc.s.nwrp = 0x1;



	for (slot = 0; slot < lfs->lfs_num; slot++)

		otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot, reg,

		otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot, reg,

				 irq_misc.u);

}
@@ -157,7 +157,7 @@ static void cptlf_enable_intrs(struct otx2_cptlfs_info *lfs) 


	/* Enable done interrupts */

	for (slot = 0; slot < lfs->lfs_num; slot++)

		otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,

		otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,

				 OTX2_CPT_LF_DONE_INT_ENA_W1S, 0x1);

	/* Enable Misc interrupts */

	cptlf_set_misc_intrs(lfs, true);
@@ -168,7 +168,7 @@ static void cptlf_disable_intrs(struct otx2_cptlfs_info *lfs) 
	int slot;



	for (slot = 0; slot < lfs->lfs_num; slot++)

		otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,

		otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,

				 OTX2_CPT_LF_DONE_INT_ENA_W1C, 0x1);

	cptlf_set_misc_intrs(lfs, false);

}
@@ -177,7 +177,7 @@ static inline int cptlf_read_done_cnt(struct otx2_cptlf_info *lf) 
{

	union otx2_cptx_lf_done irq_cnt;



	irq_cnt.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

	irq_cnt.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

				    OTX2_CPT_LF_DONE);

	return irq_cnt.s.done;

}
@@ -189,8 +189,8 @@ static irqreturn_t cptlf_misc_intr_handler(int __always_unused irq, void *arg) 
	struct device *dev;



	dev = &lf->lfs->pdev->dev;

	irq_misc.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

				     OTX2_CPT_LF_MISC_INT);

	irq_misc.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,

				     lf->slot, OTX2_CPT_LF_MISC_INT);

	irq_misc_ack.u = 0x0;



	if (irq_misc.s.fault) {
@@ -222,7 +222,7 @@ static irqreturn_t cptlf_misc_intr_handler(int __always_unused irq, void *arg) 
	}



	/* Acknowledge interrupts */

	otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

	otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

			 OTX2_CPT_LF_MISC_INT, irq_misc_ack.u);



	return IRQ_HANDLED;
@@ -237,13 +237,13 @@ static irqreturn_t cptlf_done_intr_handler(int irq, void *arg) 
	/* Read the number of completed requests */

	irq_cnt = cptlf_read_done_cnt(lf);

	if (irq_cnt) {

		done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0,

		done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,

					      lf->slot, OTX2_CPT_LF_DONE_WAIT);

		/* Acknowledge the number of completed requests */

		otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

		otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

				 OTX2_CPT_LF_DONE_ACK, irq_cnt);



		otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

		otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

				 OTX2_CPT_LF_DONE_WAIT, done_wait.u);

		if (unlikely(!lf->wqe)) {

			dev_err(&lf->lfs->pdev->dev, "No work for LF %d\n",
@@ -393,7 +393,7 @@ int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_mask, int pri, 
						 OTX2_CPT_LMT_LF_LMTLINEX(0));



		lfs->lf[slot].ioreg = lfs->reg_base +

			OTX2_CPT_RVU_FUNC_ADDR_S(BLKADDR_CPT0, slot,

			OTX2_CPT_RVU_FUNC_ADDR_S(lfs->blkaddr, slot,

						 OTX2_CPT_LF_NQX(0));

	}

	/* Send request to attach LFs */

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

+24 −9
Original line number Diff line number Diff line
@@ -180,7 +180,7 @@ static inline void otx2_cptlf_set_iqueues_base_addr( 


	for (slot = 0; slot < lfs->lfs_num; slot++) {

		lf_q_base.u = lfs->lf[slot].iqueue.dma_addr;

		otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,

		otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,

				 OTX2_CPT_LF_Q_BASE, lf_q_base.u);

	}

}
@@ -191,7 +191,7 @@ static inline void otx2_cptlf_do_set_iqueue_size(struct otx2_cptlf_info *lf) 


	lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40 +

				 OTX2_CPT_EXTRA_SIZE_DIV40;

	otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

	otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,

			 OTX2_CPT_LF_Q_SIZE, lf_q_size.u);

}
@@ -207,15 +207,16 @@ static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf) 
{

	union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 };

	union otx2_cptx_lf_inprog lf_inprog;

	u8 blkaddr = lf->lfs->blkaddr;

	int timeout = 20;



	/* Disable instructions enqueuing */

	otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

	otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,

			 OTX2_CPT_LF_CTL, lf_ctl.u);



	/* Wait for instruction queue to become empty */

	do {

		lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0,

		lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr,

					      lf->slot, OTX2_CPT_LF_INPROG);

		if (!lf_inprog.s.inflight)

			break;
@@ -234,7 +235,7 @@ static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf) 
	 * the queue should be empty at this point

	 */

	lf_inprog.s.eena = 0x0;

	otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

	otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,

			 OTX2_CPT_LF_INPROG, lf_inprog.u);

}
@@ -249,14 +250,15 @@ static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs) 
static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf,

					     bool enable)

{

	u8 blkaddr = lf->lfs->blkaddr;

	union otx2_cptx_lf_ctl lf_ctl;



	lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

	lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,

				   OTX2_CPT_LF_CTL);



	/* Set iqueue's enqueuing */

	lf_ctl.s.ena = enable ? 0x1 : 0x0;

	otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

	otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,

			 OTX2_CPT_LF_CTL, lf_ctl.u);

}
@@ -269,13 +271,14 @@ static inline void otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info *lf, 
					      bool enable)

{

	union otx2_cptx_lf_inprog lf_inprog;

	u8 blkaddr = lf->lfs->blkaddr;



	lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

	lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,

				      OTX2_CPT_LF_INPROG);



	/* Set iqueue's execution */

	lf_inprog.s.eena = enable ? 0x1 : 0x0;

	otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,

	otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,

			 OTX2_CPT_LF_INPROG, lf_inprog.u);

}
@@ -364,6 +367,18 @@ static inline bool otx2_cptlf_started(struct otx2_cptlfs_info *lfs) 
	return atomic_read(&lfs->state) == OTX2_CPTLF_STARTED;

}



static inline void otx2_cptlf_set_dev_info(struct otx2_cptlfs_info *lfs,

					   struct pci_dev *pdev,

					   void __iomem *reg_base,

					   struct otx2_mbox *mbox,

					   int blkaddr)

{

	lfs->pdev = pdev;

	lfs->reg_base = reg_base;

	lfs->mbox = mbox;

	lfs->blkaddr = blkaddr;

}



int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri,

		    int lfs_num);

void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf.h

+3 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ struct otx2_cptpf_dev { 
	struct otx2_cptvf_info vf[OTX2_CPT_MAX_VFS_NUM];

	struct otx2_cpt_eng_grps eng_grps;/* Engine groups information */

	struct otx2_cptlfs_info lfs;      /* CPT LFs attached to this PF */

	struct otx2_cptlfs_info cpt1_lfs; /* CPT1 LFs attached to this PF */

	/* HW capabilities for each engine type */

	union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES];

	bool is_eng_caps_discovered;
@@ -55,8 +56,10 @@ struct otx2_cptpf_dev { 
	u8 pf_id;               /* RVU PF number */

	u8 max_vfs;		/* Maximum number of VFs supported by CPT */

	u8 enabled_vfs;		/* Number of enabled VFs */

	u8 sso_pf_func_ovrd;	/* SSO PF_FUNC override bit */

	u8 kvf_limits;		/* Kernel crypto limits */

	bool has_cpt1;

	u8 rsrc_req_blkaddr;



	/* Devlink */

	struct devlink *dl;