Commit a46cfc0f authored by Dan Williams's avatar Dan Williams
Browse files

cxl/pmem: Introduce a find_cxl_root() helper 



In preparation for switch port enumeration while also preserving the
potential for multi-domain / multi-root CXL topologies. Introduce a
'struct device' generic mechanism for retrieving a root CXL port, if one
is registered. Note that the only known multi-domain CXL configurations
are running the cxl_test unit test on a system that also publishes an
ACPI0017 device.

With this in hand the nvdimm-bridge lookup can be with
device_find_child() instead of bus_find_device() + custom mocked lookup
infrastructure in cxl_test.

The mechanism looks for a 2nd level port since the root level topology
is platform-firmware specific and the 2nd level down follows standard
PCIe topology expectations. The cxl_acpi 2nd level is associated with a
PCIe Root Port.

Reported-by: default avatarBen Widawsky <ben.widawsky@intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/164367562182.225521.9488555616768096049.stgit@dwillia2-desk3.amr.corp.intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 5ff7316f

drivers/cxl/core/pmem.c

+10 −4
Original line number Diff line number Diff line
@@ -57,24 +57,30 @@ bool is_cxl_nvdimm_bridge(struct device *dev) 
}

EXPORT_SYMBOL_NS_GPL(is_cxl_nvdimm_bridge, CXL);



__mock int match_nvdimm_bridge(struct device *dev, const void *data)

static int match_nvdimm_bridge(struct device *dev, void *data)

{

	return is_cxl_nvdimm_bridge(dev);

}



struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_nvdimm *cxl_nvd)

{

	struct cxl_port *port = find_cxl_root(&cxl_nvd->dev);

	struct device *dev;



	dev = bus_find_device(&cxl_bus_type, NULL, cxl_nvd, match_nvdimm_bridge);

	if (!port)

		return NULL;



	dev = device_find_child(&port->dev, NULL, match_nvdimm_bridge);

	put_device(&port->dev);



	if (!dev)

		return NULL;



	return to_cxl_nvdimm_bridge(dev);

}

EXPORT_SYMBOL_NS_GPL(cxl_find_nvdimm_bridge, CXL);



static struct cxl_nvdimm_bridge *

cxl_nvdimm_bridge_alloc(struct cxl_port *port)

static struct cxl_nvdimm_bridge *cxl_nvdimm_bridge_alloc(struct cxl_port *port)

{

	struct cxl_nvdimm_bridge *cxl_nvb;

	struct device *dev;

drivers/cxl/core/port.c

+49 −0
Original line number Diff line number Diff line
@@ -455,6 +455,55 @@ int devm_cxl_register_pci_bus(struct device *host, struct device *uport, 
}

EXPORT_SYMBOL_NS_GPL(devm_cxl_register_pci_bus, CXL);



/* Find a 2nd level CXL port that has a dport that is an ancestor of @match */

static int match_root_child(struct device *dev, const void *match)

{

	const struct device *iter = NULL;

	struct cxl_port *port, *parent;

	struct cxl_dport *dport;



	if (!is_cxl_port(dev))

		return 0;



	port = to_cxl_port(dev);

	if (is_cxl_root(port))

		return 0;



	parent = to_cxl_port(port->dev.parent);

	if (!is_cxl_root(parent))

		return 0;



	cxl_device_lock(&port->dev);

	list_for_each_entry(dport, &port->dports, list) {

		iter = match;

		while (iter) {

			if (iter == dport->dport)

				goto out;

			iter = iter->parent;

		}

	}

out:

	cxl_device_unlock(&port->dev);



	return !!iter;

}



struct cxl_port *find_cxl_root(struct device *dev)

{

	struct device *port_dev;

	struct cxl_port *root;



	port_dev = bus_find_device(&cxl_bus_type, NULL, dev, match_root_child);

	if (!port_dev)

		return NULL;



	root = to_cxl_port(port_dev->parent);

	get_device(&root->dev);

	put_device(port_dev);

	return root;

}

EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL);



static struct cxl_dport *find_dport(struct cxl_port *port, int id)

{

	struct cxl_dport *dport;

drivers/cxl/cxl.h

+1 −0
Original line number Diff line number Diff line
@@ -304,6 +304,7 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, 


int cxl_add_dport(struct cxl_port *port, struct device *dport, int port_id,

		  resource_size_t component_reg_phys);

struct cxl_port *find_cxl_root(struct device *dev);



struct cxl_decoder *to_cxl_decoder(struct device *dev);

bool is_root_decoder(struct device *dev);

tools/testing/cxl/Kbuild

+0 −2
Original line number Diff line number Diff line
@@ -32,6 +32,4 @@ cxl_core-y += $(CXL_CORE_SRC)/memdev.o 
cxl_core-y += $(CXL_CORE_SRC)/mbox.o

cxl_core-y += config_check.o



cxl_core-y += mock_pmem.o



obj-m += test/

tools/testing/cxl/mock_pmem.c

deleted100644 → 0
+0 −24
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright(c) 2021 Intel Corporation. All rights reserved. */

#include <cxl.h>

#include "test/mock.h"

#include <core/core.h>



int match_nvdimm_bridge(struct device *dev, const void *data)

{

	int index, rc = 0;

	struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);

	const struct cxl_nvdimm *cxl_nvd = data;



	if (ops) {

		if (dev->type == &cxl_nvdimm_bridge_type &&

		    (ops->is_mock_dev(dev->parent->parent) ==

		     ops->is_mock_dev(cxl_nvd->dev.parent->parent)))

			rc = 1;

	} else

		rc = dev->type == &cxl_nvdimm_bridge_type;



	put_cxl_mock_ops(index);



	return rc;

}