Commit a42f0c7a authored by Joao Martins's avatar Joao Martins Committed by Joerg Roedel
Browse files

iommu/amd: Switch amd_iommu_update_ga() to use modify_irte_ga() 



The modify_irte_ga() uses cmpxchg_double() to update the IRTE in one shot,
which is necessary when adding IRTE cache disabling support since
the driver no longer need to flush the IRT for hardware to take effect.

Please note that there is a functional change where the IsRun and
Destination bits of IRTE are now cached in the struct amd_ir_data.entry.

Reviewed-by: default avatarJerry Snitselaar <jsnitsel@redhat.com>
Signed-off-by: default avatarJoao Martins <joao.m.martins@oracle.com>
Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Link: https://lore.kernel.org/r/20230530141137.14376-2-suravee.suthikulpanit@amd.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 75a61616

drivers/iommu/amd/iommu.c

+10 −28
Original line number Diff line number Diff line
@@ -3702,44 +3702,26 @@ int amd_iommu_create_irq_domain(struct amd_iommu *iommu) 


int amd_iommu_update_ga(int cpu, bool is_run, void *data)

{

	unsigned long flags;

	struct amd_iommu *iommu;

	struct irq_remap_table *table;

	struct amd_ir_data *ir_data = (struct amd_ir_data *)data;

	int devid = ir_data->irq_2_irte.devid;

	struct irte_ga *entry = (struct irte_ga *) ir_data->entry;

	struct irte_ga *ref = (struct irte_ga *) ir_data->ref;



	if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||

	    !ref || !entry || !entry->lo.fields_vapic.guest_mode)

	    !entry || !entry->lo.fields_vapic.guest_mode)

		return 0;



	iommu = ir_data->iommu;

	if (!iommu)

		return -ENODEV;



	table = get_irq_table(iommu, devid);

	if (!table)

	if (!ir_data->iommu)

		return -ENODEV;



	raw_spin_lock_irqsave(&table->lock, flags);



	if (ref->lo.fields_vapic.guest_mode) {

	if (cpu >= 0) {

			ref->lo.fields_vapic.destination =

		entry->lo.fields_vapic.destination =

					APICID_TO_IRTE_DEST_LO(cpu);

			ref->hi.fields.destination =

		entry->hi.fields.destination =

					APICID_TO_IRTE_DEST_HI(cpu);

	}

		ref->lo.fields_vapic.is_run = is_run;

		barrier();

	}



	raw_spin_unlock_irqrestore(&table->lock, flags);

	entry->lo.fields_vapic.is_run = is_run;



	iommu_flush_irt(iommu, devid);

	iommu_completion_wait(iommu);

	return 0;

	return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid,

			      ir_data->irq_2_irte.index, entry, ir_data);

}

EXPORT_SYMBOL(amd_iommu_update_ga);

#endif