Commit a41cdb69 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark
Browse files

drm/msm/dpu: make dpu_hw_ctl_clear_all_blendstages clear necessary LMs 



dpu_hw_ctl_clear_all_blendstages() clears settings for the few first LMs
instead of mixers actually used for the CTL. Change it to clear
necessary data, using provided mixer ids.

Fixes: 25fdd593 ("drm/msm: Add SDM845 DPU support")
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210704230519.4081467-1-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent f964cfb7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

+6 −4
Original line number Diff line number Diff line
@@ -345,10 +345,12 @@ static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx) 
	int i;



	for (i = 0; i < ctx->mixer_count; i++) {

		DPU_REG_WRITE(c, CTL_LAYER(LM_0 + i), 0);

		DPU_REG_WRITE(c, CTL_LAYER_EXT(LM_0 + i), 0);

		DPU_REG_WRITE(c, CTL_LAYER_EXT2(LM_0 + i), 0);

		DPU_REG_WRITE(c, CTL_LAYER_EXT3(LM_0 + i), 0);

		enum dpu_lm mixer_id = ctx->mixer_hw_caps[i].id;



		DPU_REG_WRITE(c, CTL_LAYER(mixer_id), 0);

		DPU_REG_WRITE(c, CTL_LAYER_EXT(mixer_id), 0);

		DPU_REG_WRITE(c, CTL_LAYER_EXT2(mixer_id), 0);

		DPU_REG_WRITE(c, CTL_LAYER_EXT3(mixer_id), 0);

	}



	DPU_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);