Commit a4135cbe authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Michael Ellerman
Browse files

powerpc/pseries: Stop selecting PPC_HASH_MMU_NATIVE 



The pseries platform does not use the native hash code but the PAPR
virtualised hash interfaces, so remove PPC_HASH_MMU_NATIVE.

This requires moving tlbiel code from hash_native.c to hash_utils.c.

Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211201144153.2456614-4-npiggin@gmail.com
parent 7ebc4903

arch/powerpc/include/asm/book3s/64/tlbflush.h

+0 −4
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ enum { 
	TLB_INVAL_SCOPE_LPID = 1,	/* invalidate TLBs for current LPID */

};



#ifdef CONFIG_PPC_NATIVE

static inline void tlbiel_all(void)

{

	/*
@@ -30,9 +29,6 @@ static inline void tlbiel_all(void) 
	else

		hash__tlbiel_all(TLB_INVAL_SCOPE_GLOBAL);

}

#else

static inline void tlbiel_all(void) { BUG(); }

#endif



static inline void tlbiel_all_lpid(bool radix)

{

arch/powerpc/mm/book3s64/hash_native.c

+0 −104
Original line number Diff line number Diff line
@@ -43,110 +43,6 @@ 


static DEFINE_RAW_SPINLOCK(native_tlbie_lock);



static inline void tlbiel_hash_set_isa206(unsigned int set, unsigned int is)

{

	unsigned long rb;



	rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));



	asm volatile("tlbiel %0" : : "r" (rb));

}



/*

 * tlbiel instruction for hash, set invalidation

 * i.e., r=1 and is=01 or is=10 or is=11

 */

static __always_inline void tlbiel_hash_set_isa300(unsigned int set, unsigned int is,

					unsigned int pid,

					unsigned int ric, unsigned int prs)

{

	unsigned long rb;

	unsigned long rs;

	unsigned int r = 0; /* hash format */



	rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));

	rs = ((unsigned long)pid << PPC_BITLSHIFT(31));



	asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4)

		     : : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "i"(r)

		     : "memory");

}





static void tlbiel_all_isa206(unsigned int num_sets, unsigned int is)

{

	unsigned int set;



	asm volatile("ptesync": : :"memory");



	for (set = 0; set < num_sets; set++)

		tlbiel_hash_set_isa206(set, is);



	ppc_after_tlbiel_barrier();

}



static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is)

{

	unsigned int set;



	asm volatile("ptesync": : :"memory");



	/*

	 * Flush the partition table cache if this is HV mode.

	 */

	if (early_cpu_has_feature(CPU_FTR_HVMODE))

		tlbiel_hash_set_isa300(0, is, 0, 2, 0);



	/*

	 * Now invalidate the process table cache. UPRT=0 HPT modes (what

	 * current hardware implements) do not use the process table, but

	 * add the flushes anyway.

	 *

	 * From ISA v3.0B p. 1078:

	 *     The following forms are invalid.

	 *      * PRS=1, R=0, and RIC!=2 (The only process-scoped

	 *        HPT caching is of the Process Table.)

	 */

	tlbiel_hash_set_isa300(0, is, 0, 2, 1);



	/*

	 * Then flush the sets of the TLB proper. Hash mode uses

	 * partition scoped TLB translations, which may be flushed

	 * in !HV mode.

	 */

	for (set = 0; set < num_sets; set++)

		tlbiel_hash_set_isa300(set, is, 0, 0, 0);



	ppc_after_tlbiel_barrier();



	asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT "; isync" : : :"memory");

}



void hash__tlbiel_all(unsigned int action)

{

	unsigned int is;



	switch (action) {

	case TLB_INVAL_SCOPE_GLOBAL:

		is = 3;

		break;

	case TLB_INVAL_SCOPE_LPID:

		is = 2;

		break;

	default:

		BUG();

	}



	if (early_cpu_has_feature(CPU_FTR_ARCH_300))

		tlbiel_all_isa300(POWER9_TLB_SETS_HASH, is);

	else if (early_cpu_has_feature(CPU_FTR_ARCH_207S))

		tlbiel_all_isa206(POWER8_TLB_SETS, is);

	else if (early_cpu_has_feature(CPU_FTR_ARCH_206))

		tlbiel_all_isa206(POWER7_TLB_SETS, is);

	else

		WARN(1, "%s called on pre-POWER7 CPU\n", __func__);

}



static inline unsigned long  ___tlbie(unsigned long vpn, int psize,

						int apsize, int ssize)

{

arch/powerpc/mm/book3s64/hash_utils.c

+104 −0
Original line number Diff line number Diff line
@@ -175,6 +175,110 @@ static struct mmu_psize_def mmu_psize_defaults_gp[] = { 
	},

};



static inline void tlbiel_hash_set_isa206(unsigned int set, unsigned int is)

{

	unsigned long rb;



	rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));



	asm volatile("tlbiel %0" : : "r" (rb));

}



/*

 * tlbiel instruction for hash, set invalidation

 * i.e., r=1 and is=01 or is=10 or is=11

 */

static __always_inline void tlbiel_hash_set_isa300(unsigned int set, unsigned int is,

					unsigned int pid,

					unsigned int ric, unsigned int prs)

{

	unsigned long rb;

	unsigned long rs;

	unsigned int r = 0; /* hash format */



	rb = (set << PPC_BITLSHIFT(51)) | (is << PPC_BITLSHIFT(53));

	rs = ((unsigned long)pid << PPC_BITLSHIFT(31));



	asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4)

		     : : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "i"(r)

		     : "memory");

}





static void tlbiel_all_isa206(unsigned int num_sets, unsigned int is)

{

	unsigned int set;



	asm volatile("ptesync": : :"memory");



	for (set = 0; set < num_sets; set++)

		tlbiel_hash_set_isa206(set, is);



	ppc_after_tlbiel_barrier();

}



static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is)

{

	unsigned int set;



	asm volatile("ptesync": : :"memory");



	/*

	 * Flush the partition table cache if this is HV mode.

	 */

	if (early_cpu_has_feature(CPU_FTR_HVMODE))

		tlbiel_hash_set_isa300(0, is, 0, 2, 0);



	/*

	 * Now invalidate the process table cache. UPRT=0 HPT modes (what

	 * current hardware implements) do not use the process table, but

	 * add the flushes anyway.

	 *

	 * From ISA v3.0B p. 1078:

	 *     The following forms are invalid.

	 *      * PRS=1, R=0, and RIC!=2 (The only process-scoped

	 *        HPT caching is of the Process Table.)

	 */

	tlbiel_hash_set_isa300(0, is, 0, 2, 1);



	/*

	 * Then flush the sets of the TLB proper. Hash mode uses

	 * partition scoped TLB translations, which may be flushed

	 * in !HV mode.

	 */

	for (set = 0; set < num_sets; set++)

		tlbiel_hash_set_isa300(set, is, 0, 0, 0);



	ppc_after_tlbiel_barrier();



	asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT "; isync" : : :"memory");

}



void hash__tlbiel_all(unsigned int action)

{

	unsigned int is;



	switch (action) {

	case TLB_INVAL_SCOPE_GLOBAL:

		is = 3;

		break;

	case TLB_INVAL_SCOPE_LPID:

		is = 2;

		break;

	default:

		BUG();

	}



	if (early_cpu_has_feature(CPU_FTR_ARCH_300))

		tlbiel_all_isa300(POWER9_TLB_SETS_HASH, is);

	else if (early_cpu_has_feature(CPU_FTR_ARCH_207S))

		tlbiel_all_isa206(POWER8_TLB_SETS, is);

	else if (early_cpu_has_feature(CPU_FTR_ARCH_206))

		tlbiel_all_isa206(POWER7_TLB_SETS, is);

	else

		WARN(1, "%s called on pre-POWER7 CPU\n", __func__);

}



/*

 * 'R' and 'C' update notes:

 *  - Under pHyp or KVM, the updatepp path will not set C, thus it *will*

arch/powerpc/platforms/pseries/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -17,7 +17,6 @@ config PPC_PSERIES 
	select PPC_RTAS_DAEMON

	select RTAS_ERROR_LOGGING

	select PPC_UDBG_16550

	select PPC_HASH_MMU_NATIVE

	select PPC_DOORBELL

	select HOTPLUG_CPU

	select ARCH_RANDOM