Commit a3efabee authored by Andrzej Kacprowski's avatar Andrzej Kacprowski Committed by Stanislaw Gruszka
Browse files

accel/ivpu: Fix sporadic VPU boot failure 



Wait for AON bit in HOST_SS_CPR_RST_CLR to return 0 before
starting VPUIP power up sequence, otherwise the VPU device
may sporadically fail to boot.

An error in power up sequence is propagated to the runtime
power management - the device will be in an error state
until the VPU driver is reloaded.

Fixes: 35b13763 ("accel/ivpu: Introduce a new DRM driver for Intel VPU")
Cc: stable@vger.kernel.org # 6.3.x
Signed-off-by: default avatarAndrzej Kacprowski <andrzej.kacprowski@linux.intel.com>
Reviewed-by: default avatarKrystian Pradzynski <krystian.pradzynski@linux.intel.com>
Signed-off-by: default avatarStanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230607094502.388489-1-stanislaw.gruszka@linux.intel.com
parent b563e479

drivers/accel/ivpu/ivpu_hw_mtl.c

+12 −1
Original line number Diff line number Diff line
@@ -197,6 +197,11 @@ static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev) 
	hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);

}



static int ivpu_hw_mtl_wait_for_vpuip_bar(struct ivpu_device *vdev)

{

	return REGV_POLL_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, AON, 0, 100);

}



static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable)

{

	struct ivpu_hw_info *hw = vdev->hw;
@@ -239,6 +244,12 @@ static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable) 
			ivpu_err(vdev, "Timed out waiting for PLL ready status\n");

			return ret;

		}



		ret = ivpu_hw_mtl_wait_for_vpuip_bar(vdev);

		if (ret) {

			ivpu_err(vdev, "Timed out waiting for VPUIP bar\n");

			return ret;

		}

	}



	return 0;
@@ -256,7 +267,7 @@ static int ivpu_pll_disable(struct ivpu_device *vdev) 


static void ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device *vdev)

{

	u32 val = REGV_RD32(MTL_VPU_HOST_SS_CPR_RST_CLR);

	u32 val = 0;



	val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, TOP_NOC, val);

	val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, DSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_mtl_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ 
#define MTL_VPU_HOST_SS_CPR_RST_SET_MSS_MAS_MASK			BIT_MASK(11)



#define MTL_VPU_HOST_SS_CPR_RST_CLR					0x00000098u

#define MTL_VPU_HOST_SS_CPR_RST_CLR_AON_MASK				BIT_MASK(0)

#define MTL_VPU_HOST_SS_CPR_RST_CLR_TOP_NOC_MASK			BIT_MASK(1)

#define MTL_VPU_HOST_SS_CPR_RST_CLR_DSS_MAS_MASK			BIT_MASK(10)

#define MTL_VPU_HOST_SS_CPR_RST_CLR_MSS_MAS_MASK			BIT_MASK(11)