Commit a3e77b70 authored by Sander Vanheule's avatar Sander Vanheule Committed by Marc Zyngier
Browse files

dt-bindings: interrupt-controller: realtek,rtl-intc: require parents 



The interrupt router has 32 inputs, and up to 15 outputs connected to
the MIPS CPU's interrupts. The way these are mapped to each other is
runtime configurable. This controller can also mask individual interrupt
sources, and has a status register to indicate pending interrupts. This
means the controller is not transparent, and the use of "interrupt-map"
inappropriate. Instead, a list of parent interrupts should be specified.

Two-part compatibles are introduced to be able to require "interrupts"
for new devicetrees. For backward compatibility "interrupt-map" is still
allowed on these new compatibles, but deprecated. The old compatible,
with required "interrupt-map" and "#address-cells", is also deprecated.
The relevant descriptions are added or extended to more clearly describe
the functionality of this controller.

To prevent spurious changes to the binding when more SoCs are added,
"allOf" is used with one "if", and the compatible enum only has one
item.

The example is updated to provide a correct example for RTL8380 SoCs.

Signed-off-by: default avatarSander Vanheule <sander@svanheule.net>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/ba3ae8e521ef82dd94f18a602ef53078f4a0d8d5.1663617425.git.sander@svanheule.net
parent a1cc8a62

Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml

+45 −15
Original line number Diff line number Diff line
@@ -6,6 +6,14 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 


title: Realtek RTL SoC interrupt controller devicetree bindings



description:

  Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC

  interrupt to be routed to one parent CPU (hardware) interrupt, or left

  disconnected.

  All connected input lines from SoC peripherals can be masked individually,

  and an interrupt status register is present to indicate which interrupts are

  pending.



maintainers:

  - Birger Koblitz <mail@birger-koblitz.de>

  - Bert Vermeulen <bert@biot.com>
@@ -13,23 +21,33 @@ maintainers: 


properties:

  compatible:

    const: realtek,rtl-intc

    oneOf:

      - items:

          - enum:

              - realtek,rtl8380-intc

          - const: realtek,rtl-intc

      - const: realtek,rtl-intc

        deprecated: true



  "#interrupt-cells":

    description:

      SoC interrupt line index.

    const: 1



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1

    minItems: 1

    maxItems: 15

    description:

      List of parent interrupts, in the order that they are connected to this

      interrupt router's outputs, starting at the first output.



  interrupt-controller: true



  "#address-cells":

    const: 0



  interrupt-map:

    deprecated: true

    description: Describes mapping from SoC interrupts to CPU interrupts



required:
@@ -37,21 +55,33 @@ required: 
  - reg

  - "#interrupt-cells"

  - interrupt-controller



allOf:

  - if:

      properties:

        compatible:

          const: realtek,rtl-intc

    then:

      properties:

        "#address-cells":

          const: 0

      required:

        - "#address-cells"

        - interrupt-map

    else:

      required:

        - interrupts



additionalProperties: false



examples:

  - |

    intc: interrupt-controller@3000 {

      compatible = "realtek,rtl-intc";

    interrupt-controller@3000 {

      compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";

      #interrupt-cells = <1>;

      interrupt-controller;

      reg = <0x3000 0x20>;

      #address-cells = <0>;

      interrupt-map =

              <31 &cpuintc 2>,

              <30 &cpuintc 1>,

              <29 &cpuintc 5>;

      reg = <0x3000 0x18>;



      interrupt-parent = <&cpuintc>;

      interrupts = <2>, <3>, <4>, <5>, <6>;

    };