Commit a3e23092 authored by Christoph Hellwig's avatar Christoph Hellwig
Browse files

x86: centralize setting SWIOTLB_FORCE when guest memory encryption is enabled



Move enabling SWIOTLB_FORCE for guest memory encryption into common code.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Reviewed-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Tested-by: default avatarBoris Ostrovsky <boris.ostrovsky@oracle.com>
parent 78013eaa
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+0 −8
Original line number Diff line number Diff line
@@ -337,14 +337,6 @@ static void __init ms_hyperv_init_platform(void)
			swiotlb_unencrypted_base = ms_hyperv.shared_gpa_boundary;
#endif
		}

#ifdef CONFIG_SWIOTLB
		/*
		 * Enable swiotlb force mode in Isolation VM to
		 * use swiotlb bounce buffer for dma transaction.
		 */
		swiotlb_force = SWIOTLB_FORCE;
#endif
		/* Isolation VMs are unenlightened SEV-based VMs, thus this check: */
		if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) {
			if (hv_get_isolation_type() != HV_ISOLATION_TYPE_NONE)
+8 −0
Original line number Diff line number Diff line
@@ -53,6 +53,14 @@ static void __init pci_swiotlb_detect(void)
	if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT))
		x86_swiotlb_enable = true;

	/*
	 * Guest with guest memory encryption currently perform all DMA through
	 * bounce buffers as the hypervisor can't access arbitrary VM memory
	 * that is not explicitly shared with it.
	 */
	if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT))
		swiotlb_force = SWIOTLB_FORCE;

	if (swiotlb_force == SWIOTLB_FORCE)
		x86_swiotlb_enable = true;
}
+0 −3
Original line number Diff line number Diff line
@@ -432,9 +432,6 @@ void __init sme_early_init(void)
	for (i = 0; i < ARRAY_SIZE(protection_map); i++)
		protection_map[i] = pgprot_encrypted(protection_map[i]);

	if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT))
		swiotlb_force = SWIOTLB_FORCE;

	x86_platform.guest.enc_status_change_prepare = amd_enc_status_change_prepare;
	x86_platform.guest.enc_status_change_finish  = amd_enc_status_change_finish;
	x86_platform.guest.enc_tlb_flush_required    = amd_enc_tlb_flush_required;