Commit a3d0245c authored by Max Filippov's avatar Max Filippov
Browse files

xtensa: fix xtensa_wsr always writing 0 



The commit cad6fade ("xtensa: clean up WSR*/RSR*/get_sr/set_sr")
replaced 'WSR' macro in the function xtensa_wsr with 'xtensa_set_sr',
but variable 'v' in the xtensa_set_sr body shadowed the argument 'v'
passed to it, resulting in wrong value written to debug registers.

Fix that by removing intermediate variable from the xtensa_set_sr
macro body.

Cc: stable@vger.kernel.org
Fixes: cad6fade ("xtensa: clean up WSR*/RSR*/get_sr/set_sr")
Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
parent 7dc0eb0b

arch/xtensa/include/asm/processor.h

+2 −2
Original line number Diff line number Diff line
@@ -242,8 +242,8 @@ extern unsigned long __get_wchan(struct task_struct *p); 


#define xtensa_set_sr(x, sr) \

	({ \

	 unsigned int v = (unsigned int)(x); \

	 __asm__ __volatile__ ("wsr %0, "__stringify(sr) :: "a"(v)); \

	 __asm__ __volatile__ ("wsr %0, "__stringify(sr) :: \

			       "a"((unsigned int)(x))); \

	 })



#define xtensa_get_sr(sr) \