Commit a3b355c7 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'qca8k-phylink' 



Russell King says:

====================
net: dsa: qca8k: convert to phylink_pcs and mark as non-legacy

This series adds support into DSA for the mac_select_pcs method, and
converts qca8k to make use of this, eventually marking qca8k as non-
legacy.

Patch 1 adds DSA support for mac_select_pcs.
Patch 2 and patch 3 moves code around in qca8k to make patch 4 more
readable.
Patch 4 does a simple conversion to phylink_pcs.
Patch 5 moves the serdes configuration to phylink_pcs.
Patch 6 marks qca8k as non-legacy.

v2: fix dsa_phylink_mac_select_pcs() formatting and double-blank line
in patch 5
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 8aba73ef d9cbacf0

drivers/net/dsa/qca8k.c

+409 −328
Original line number Diff line number Diff line
@@ -1632,220 +1632,6 @@ qca8k_parse_port_config(struct qca8k_priv *priv) 
	return 0;

}



static int

qca8k_setup(struct dsa_switch *ds)

{

	struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;

	int cpu_port, ret, i;

	u32 mask;



	cpu_port = qca8k_find_cpu_port(ds);

	if (cpu_port < 0) {

		dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");

		return cpu_port;

	}



	/* Parse CPU port config to be later used in phy_link mac_config */

	ret = qca8k_parse_port_config(priv);

	if (ret)

		return ret;



	ret = qca8k_setup_mdio_bus(priv);

	if (ret)

		return ret;



	ret = qca8k_setup_of_pws_reg(priv);

	if (ret)

		return ret;



	ret = qca8k_setup_mac_pwr_sel(priv);

	if (ret)

		return ret;



	/* Make sure MAC06 is disabled */

	ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,

				QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);

	if (ret) {

		dev_err(priv->dev, "failed disabling MAC06 exchange");

		return ret;

	}



	/* Enable CPU Port */

	ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,

			      QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);

	if (ret) {

		dev_err(priv->dev, "failed enabling CPU port");

		return ret;

	}



	/* Enable MIB counters */

	ret = qca8k_mib_init(priv);

	if (ret)

		dev_warn(priv->dev, "mib init failed");



	/* Initial setup of all ports */

	for (i = 0; i < QCA8K_NUM_PORTS; i++) {

		/* Disable forwarding by default on all ports */

		ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),

				QCA8K_PORT_LOOKUP_MEMBER, 0);

		if (ret)

			return ret;



		/* Enable QCA header mode on all cpu ports */

		if (dsa_is_cpu_port(ds, i)) {

			ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),

					  FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |

					  FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));

			if (ret) {

				dev_err(priv->dev, "failed enabling QCA header mode");

				return ret;

			}

		}



		/* Disable MAC by default on all user ports */

		if (dsa_is_user_port(ds, i))

			qca8k_port_set_status(priv, i, 0);

	}



	/* Forward all unknown frames to CPU port for Linux processing

	 * Notice that in multi-cpu config only one port should be set

	 * for igmp, unknown, multicast and broadcast packet

	 */

	ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,

			  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |

			  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |

			  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |

			  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));

	if (ret)

		return ret;



	/* Setup connection between CPU port & user ports

	 * Configure specific switch configuration for ports

	 */

	for (i = 0; i < QCA8K_NUM_PORTS; i++) {

		/* CPU port gets connected to all user ports of the switch */

		if (dsa_is_cpu_port(ds, i)) {

			ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),

					QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));

			if (ret)

				return ret;

		}



		/* Individual user ports get connected to CPU port only */

		if (dsa_is_user_port(ds, i)) {

			ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),

					QCA8K_PORT_LOOKUP_MEMBER,

					BIT(cpu_port));

			if (ret)

				return ret;



			/* Enable ARP Auto-learning by default */

			ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i),

					      QCA8K_PORT_LOOKUP_LEARN);

			if (ret)

				return ret;



			/* For port based vlans to work we need to set the

			 * default egress vid

			 */

			ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),

					QCA8K_EGREES_VLAN_PORT_MASK(i),

					QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));

			if (ret)

				return ret;



			ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),

					  QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |

					  QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));

			if (ret)

				return ret;

		}



		/* The port 5 of the qca8337 have some problem in flood condition. The

		 * original legacy driver had some specific buffer and priority settings

		 * for the different port suggested by the QCA switch team. Add this

		 * missing settings to improve switch stability under load condition.

		 * This problem is limited to qca8337 and other qca8k switch are not affected.

		 */

		if (priv->switch_id == QCA8K_ID_QCA8337) {

			switch (i) {

			/* The 2 CPU port and port 5 requires some different

			 * priority than any other ports.

			 */

			case 0:

			case 5:

			case 6:

				mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |

					QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);

				break;

			default:

				mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |

					QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);

			}

			qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);



			mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |

			QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |

			QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |

			QCA8K_PORT_HOL_CTRL1_WRED_EN;

			qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),

				  QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |

				  QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |

				  QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |

				  QCA8K_PORT_HOL_CTRL1_WRED_EN,

				  mask);

		}



		/* Set initial MTU for every port.

		 * We have only have a general MTU setting. So track

		 * every port and set the max across all port.

		 * Set per port MTU to 1500 as the MTU change function

		 * will add the overhead and if its set to 1518 then it

		 * will apply the overhead again and we will end up with

		 * MTU of 1536 instead of 1518

		 */

		priv->port_mtu[i] = ETH_DATA_LEN;

	}



	/* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */

	if (priv->switch_id == QCA8K_ID_QCA8327) {

		mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |

		       QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);

		qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,

			  QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |

			  QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,

			  mask);

	}



	/* Setup our port MTUs to match power on defaults */

	ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);

	if (ret)

		dev_warn(priv->dev, "failed setting MTU settings");



	/* Flush the FDB table */

	qca8k_fdb_flush(priv);



	/* We don't have interrupts for link changes, so we need to poll */

	ds->pcs_poll = true;



	/* Set min a max ageing value supported */

	ds->ageing_time_min = 7000;

	ds->ageing_time_max = 458745000;



	/* Set max number of LAGs supported */

	ds->num_lag_ids = QCA8K_NUM_LAGS;



	return 0;

}



static void

qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,

				      u32 reg)
@@ -1887,13 +1673,41 @@ qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_inde 
			cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);

}



static struct phylink_pcs *

qca8k_phylink_mac_select_pcs(struct dsa_switch *ds, int port,

			     phy_interface_t interface)

{

	struct qca8k_priv *priv = ds->priv;

	struct phylink_pcs *pcs = NULL;



	switch (interface) {

	case PHY_INTERFACE_MODE_SGMII:

	case PHY_INTERFACE_MODE_1000BASEX:

		switch (port) {

		case 0:

			pcs = &priv->pcs_port_0.pcs;

			break;



		case 6:

			pcs = &priv->pcs_port_6.pcs;

			break;

		}

		break;



	default:

		break;

	}



	return pcs;

}



static void

qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,

			 const struct phylink_link_state *state)

{

	struct qca8k_priv *priv = ds->priv;

	int cpu_port_index, ret;

	u32 reg, val;

	int cpu_port_index;

	u32 reg;



	switch (port) {

	case 0: /* 1st CPU port */
@@ -1959,70 +1773,6 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 
	case PHY_INTERFACE_MODE_1000BASEX:

		/* Enable SGMII on the port */

		qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);



		/* Enable/disable SerDes auto-negotiation as necessary */

		ret = qca8k_read(priv, QCA8K_REG_PWS, &val);

		if (ret)

			return;

		if (phylink_autoneg_inband(mode))

			val &= ~QCA8K_PWS_SERDES_AEN_DIS;

		else

			val |= QCA8K_PWS_SERDES_AEN_DIS;

		qca8k_write(priv, QCA8K_REG_PWS, val);



		/* Configure the SGMII parameters */

		ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);

		if (ret)

			return;



		val |= QCA8K_SGMII_EN_SD;



		if (priv->ports_config.sgmii_enable_pll)

			val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |

			       QCA8K_SGMII_EN_TX;



		if (dsa_is_cpu_port(ds, port)) {

			/* CPU port, we're talking to the CPU MAC, be a PHY */

			val &= ~QCA8K_SGMII_MODE_CTRL_MASK;

			val |= QCA8K_SGMII_MODE_CTRL_PHY;

		} else if (state->interface == PHY_INTERFACE_MODE_SGMII) {

			val &= ~QCA8K_SGMII_MODE_CTRL_MASK;

			val |= QCA8K_SGMII_MODE_CTRL_MAC;

		} else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {

			val &= ~QCA8K_SGMII_MODE_CTRL_MASK;

			val |= QCA8K_SGMII_MODE_CTRL_BASEX;

		}



		qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);



		/* From original code is reported port instability as SGMII also

		 * require delay set. Apply advised values here or take them from DT.

		 */

		if (state->interface == PHY_INTERFACE_MODE_SGMII)

			qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);



		/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and

		 * falling edge is set writing in the PORT0 PAD reg

		 */

		if (priv->switch_id == QCA8K_ID_QCA8327 ||

		    priv->switch_id == QCA8K_ID_QCA8337)

			reg = QCA8K_REG_PORT0_PAD_CTRL;



		val = 0;



		/* SGMII Clock phase configuration */

		if (priv->ports_config.sgmii_rx_clk_falling_edge)

			val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;



		if (priv->ports_config.sgmii_tx_clk_falling_edge)

			val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;



		if (val)

			ret = qca8k_rmw(priv, reg,

					QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |

					QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,

					val);



		break;

	default:

		dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
@@ -2064,19 +1814,78 @@ static void qca8k_phylink_get_caps(struct dsa_switch *ds, int port, 


	config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |

		MAC_10 | MAC_100 | MAC_1000FD;



	config->legacy_pre_march2020 = false;

}



static int

qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,

			     struct phylink_link_state *state)

static void

qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,

			    phy_interface_t interface)

{

	struct qca8k_priv *priv = ds->priv;



	qca8k_port_set_status(priv, port, 0);

}



static void

qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,

			  phy_interface_t interface, struct phy_device *phydev,

			  int speed, int duplex, bool tx_pause, bool rx_pause)

{

	struct qca8k_priv *priv = ds->priv;

	u32 reg;



	if (phylink_autoneg_inband(mode)) {

		reg = QCA8K_PORT_STATUS_LINK_AUTO;

	} else {

		switch (speed) {

		case SPEED_10:

			reg = QCA8K_PORT_STATUS_SPEED_10;

			break;

		case SPEED_100:

			reg = QCA8K_PORT_STATUS_SPEED_100;

			break;

		case SPEED_1000:

			reg = QCA8K_PORT_STATUS_SPEED_1000;

			break;

		default:

			reg = QCA8K_PORT_STATUS_LINK_AUTO;

			break;

		}



		if (duplex == DUPLEX_FULL)

			reg |= QCA8K_PORT_STATUS_DUPLEX;



		if (rx_pause || dsa_is_cpu_port(ds, port))

			reg |= QCA8K_PORT_STATUS_RXFLOW;



		if (tx_pause || dsa_is_cpu_port(ds, port))

			reg |= QCA8K_PORT_STATUS_TXFLOW;

	}



	reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;



	qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);

}



static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs)

{

	return container_of(pcs, struct qca8k_pcs, pcs);

}



static void qca8k_pcs_get_state(struct phylink_pcs *pcs,

				struct phylink_link_state *state)

{

	struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;

	int port = pcs_to_qca8k_pcs(pcs)->port;

	u32 reg;

	int ret;



	ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);

	if (ret < 0)

		return ret;

	if (ret < 0) {

		state->link = false;

		return;

	}



	state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);

	state->an_complete = state->link;
@@ -2099,63 +1908,121 @@ qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port, 
		break;

	}



	state->pause = MLO_PAUSE_NONE;

	if (reg & QCA8K_PORT_STATUS_RXFLOW)

		state->pause |= MLO_PAUSE_RX;

	if (reg & QCA8K_PORT_STATUS_TXFLOW)

		state->pause |= MLO_PAUSE_TX;



	return 1;

}



static void

qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,

			    phy_interface_t interface)

static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int mode,

			    phy_interface_t interface,

			    const unsigned long *advertising,

			    bool permit_pause_to_mac)

{

	struct qca8k_priv *priv = ds->priv;

	struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;

	int cpu_port_index, ret, port;

	u32 reg, val;



	port = pcs_to_qca8k_pcs(pcs)->port;

	switch (port) {

	case 0:

		reg = QCA8K_REG_PORT0_PAD_CTRL;

		cpu_port_index = QCA8K_CPU_PORT0;

		break;



	case 6:

		reg = QCA8K_REG_PORT6_PAD_CTRL;

		cpu_port_index = QCA8K_CPU_PORT6;

		break;



	default:

		WARN_ON(1);

	}



	/* Enable/disable SerDes auto-negotiation as necessary */

	ret = qca8k_read(priv, QCA8K_REG_PWS, &val);

	if (ret)

		return ret;

	if (phylink_autoneg_inband(mode))

		val &= ~QCA8K_PWS_SERDES_AEN_DIS;

	else

		val |= QCA8K_PWS_SERDES_AEN_DIS;

	qca8k_write(priv, QCA8K_REG_PWS, val);



	/* Configure the SGMII parameters */

	ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);

	if (ret)

		return ret;



	val |= QCA8K_SGMII_EN_SD;



	if (priv->ports_config.sgmii_enable_pll)

		val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |

		       QCA8K_SGMII_EN_TX;



	if (dsa_is_cpu_port(priv->ds, port)) {

		/* CPU port, we're talking to the CPU MAC, be a PHY */

		val &= ~QCA8K_SGMII_MODE_CTRL_MASK;

		val |= QCA8K_SGMII_MODE_CTRL_PHY;

	} else if (interface == PHY_INTERFACE_MODE_SGMII) {

		val &= ~QCA8K_SGMII_MODE_CTRL_MASK;

		val |= QCA8K_SGMII_MODE_CTRL_MAC;

	} else if (interface == PHY_INTERFACE_MODE_1000BASEX) {

		val &= ~QCA8K_SGMII_MODE_CTRL_MASK;

		val |= QCA8K_SGMII_MODE_CTRL_BASEX;

	}



	qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);



	/* From original code is reported port instability as SGMII also

	 * require delay set. Apply advised values here or take them from DT.

	 */

	if (interface == PHY_INTERFACE_MODE_SGMII)

		qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);

	/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and

	 * falling edge is set writing in the PORT0 PAD reg

	 */

	if (priv->switch_id == QCA8K_ID_QCA8327 ||

	    priv->switch_id == QCA8K_ID_QCA8337)

		reg = QCA8K_REG_PORT0_PAD_CTRL;



	val = 0;



	/* SGMII Clock phase configuration */

	if (priv->ports_config.sgmii_rx_clk_falling_edge)

		val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;



	if (priv->ports_config.sgmii_tx_clk_falling_edge)

		val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;



	if (val)

		ret = qca8k_rmw(priv, reg,

				QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |

				QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,

				val);



	qca8k_port_set_status(priv, port, 0);

	return 0;

}



static void

qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,

			  phy_interface_t interface, struct phy_device *phydev,

			  int speed, int duplex, bool tx_pause, bool rx_pause)

static void qca8k_pcs_an_restart(struct phylink_pcs *pcs)

{

	struct qca8k_priv *priv = ds->priv;

	u32 reg;



	if (phylink_autoneg_inband(mode)) {

		reg = QCA8K_PORT_STATUS_LINK_AUTO;

	} else {

		switch (speed) {

		case SPEED_10:

			reg = QCA8K_PORT_STATUS_SPEED_10;

			break;

		case SPEED_100:

			reg = QCA8K_PORT_STATUS_SPEED_100;

			break;

		case SPEED_1000:

			reg = QCA8K_PORT_STATUS_SPEED_1000;

			break;

		default:

			reg = QCA8K_PORT_STATUS_LINK_AUTO;

			break;

}



		if (duplex == DUPLEX_FULL)

			reg |= QCA8K_PORT_STATUS_DUPLEX;



		if (rx_pause || dsa_is_cpu_port(ds, port))

			reg |= QCA8K_PORT_STATUS_RXFLOW;



		if (tx_pause || dsa_is_cpu_port(ds, port))

			reg |= QCA8K_PORT_STATUS_TXFLOW;

	}

static const struct phylink_pcs_ops qca8k_pcs_ops = {

	.pcs_get_state = qca8k_pcs_get_state,

	.pcs_config = qca8k_pcs_config,

	.pcs_an_restart = qca8k_pcs_an_restart,

};



	reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;

static void qca8k_setup_pcs(struct qca8k_priv *priv, struct qca8k_pcs *qpcs,

			    int port)

{

	qpcs->pcs.ops = &qca8k_pcs_ops;



	qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);

	/* We don't have interrupts for link changes, so we need to poll */

	qpcs->pcs.poll = true;

	qpcs->priv = priv;

	qpcs->port = port;

}



static void
@@ -2990,6 +2857,220 @@ static int qca8k_connect_tag_protocol(struct dsa_switch *ds, 
	return 0;

}



static int

qca8k_setup(struct dsa_switch *ds)

{

	struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;

	int cpu_port, ret, i;

	u32 mask;



	cpu_port = qca8k_find_cpu_port(ds);

	if (cpu_port < 0) {

		dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");

		return cpu_port;

	}



	/* Parse CPU port config to be later used in phy_link mac_config */

	ret = qca8k_parse_port_config(priv);

	if (ret)

		return ret;



	ret = qca8k_setup_mdio_bus(priv);

	if (ret)

		return ret;



	ret = qca8k_setup_of_pws_reg(priv);

	if (ret)

		return ret;



	ret = qca8k_setup_mac_pwr_sel(priv);

	if (ret)

		return ret;



	qca8k_setup_pcs(priv, &priv->pcs_port_0, 0);

	qca8k_setup_pcs(priv, &priv->pcs_port_6, 6);



	/* Make sure MAC06 is disabled */

	ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,

				QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);

	if (ret) {

		dev_err(priv->dev, "failed disabling MAC06 exchange");

		return ret;

	}



	/* Enable CPU Port */

	ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,

			      QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);

	if (ret) {

		dev_err(priv->dev, "failed enabling CPU port");

		return ret;

	}



	/* Enable MIB counters */

	ret = qca8k_mib_init(priv);

	if (ret)

		dev_warn(priv->dev, "mib init failed");



	/* Initial setup of all ports */

	for (i = 0; i < QCA8K_NUM_PORTS; i++) {

		/* Disable forwarding by default on all ports */

		ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),

				QCA8K_PORT_LOOKUP_MEMBER, 0);

		if (ret)

			return ret;



		/* Enable QCA header mode on all cpu ports */

		if (dsa_is_cpu_port(ds, i)) {

			ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),

					  FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |

					  FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));

			if (ret) {

				dev_err(priv->dev, "failed enabling QCA header mode");

				return ret;

			}

		}



		/* Disable MAC by default on all user ports */

		if (dsa_is_user_port(ds, i))

			qca8k_port_set_status(priv, i, 0);

	}



	/* Forward all unknown frames to CPU port for Linux processing

	 * Notice that in multi-cpu config only one port should be set

	 * for igmp, unknown, multicast and broadcast packet

	 */

	ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,

			  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |

			  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |

			  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |

			  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));

	if (ret)

		return ret;



	/* Setup connection between CPU port & user ports

	 * Configure specific switch configuration for ports

	 */

	for (i = 0; i < QCA8K_NUM_PORTS; i++) {

		/* CPU port gets connected to all user ports of the switch */

		if (dsa_is_cpu_port(ds, i)) {

			ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),

					QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));

			if (ret)

				return ret;

		}



		/* Individual user ports get connected to CPU port only */

		if (dsa_is_user_port(ds, i)) {

			ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),

					QCA8K_PORT_LOOKUP_MEMBER,

					BIT(cpu_port));

			if (ret)

				return ret;



			/* Enable ARP Auto-learning by default */

			ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i),

					      QCA8K_PORT_LOOKUP_LEARN);

			if (ret)

				return ret;



			/* For port based vlans to work we need to set the

			 * default egress vid

			 */

			ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),

					QCA8K_EGREES_VLAN_PORT_MASK(i),

					QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));

			if (ret)

				return ret;



			ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),

					  QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |

					  QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));

			if (ret)

				return ret;

		}



		/* The port 5 of the qca8337 have some problem in flood condition. The

		 * original legacy driver had some specific buffer and priority settings

		 * for the different port suggested by the QCA switch team. Add this

		 * missing settings to improve switch stability under load condition.

		 * This problem is limited to qca8337 and other qca8k switch are not affected.

		 */

		if (priv->switch_id == QCA8K_ID_QCA8337) {

			switch (i) {

			/* The 2 CPU port and port 5 requires some different

			 * priority than any other ports.

			 */

			case 0:

			case 5:

			case 6:

				mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |

					QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);

				break;

			default:

				mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |

					QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |

					QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);

			}

			qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);



			mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |

			QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |

			QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |

			QCA8K_PORT_HOL_CTRL1_WRED_EN;

			qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),

				  QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |

				  QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |

				  QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |

				  QCA8K_PORT_HOL_CTRL1_WRED_EN,

				  mask);

		}



		/* Set initial MTU for every port.

		 * We have only have a general MTU setting. So track

		 * every port and set the max across all port.

		 * Set per port MTU to 1500 as the MTU change function

		 * will add the overhead and if its set to 1518 then it

		 * will apply the overhead again and we will end up with

		 * MTU of 1536 instead of 1518

		 */

		priv->port_mtu[i] = ETH_DATA_LEN;

	}



	/* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */

	if (priv->switch_id == QCA8K_ID_QCA8327) {

		mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |

		       QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);

		qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,

			  QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |

			  QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,

			  mask);

	}



	/* Setup our port MTUs to match power on defaults */

	ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);

	if (ret)

		dev_warn(priv->dev, "failed setting MTU settings");



	/* Flush the FDB table */

	qca8k_fdb_flush(priv);



	/* Set min a max ageing value supported */

	ds->ageing_time_min = 7000;

	ds->ageing_time_max = 458745000;



	/* Set max number of LAGs supported */

	ds->num_lag_ids = QCA8K_NUM_LAGS;



	return 0;

}



static const struct dsa_switch_ops qca8k_switch_ops = {

	.get_tag_protocol	= qca8k_get_tag_protocol,

	.setup			= qca8k_setup,
@@ -3018,7 +3099,7 @@ static const struct dsa_switch_ops qca8k_switch_ops = { 
	.port_vlan_add		= qca8k_port_vlan_add,

	.port_vlan_del		= qca8k_port_vlan_del,

	.phylink_get_caps	= qca8k_phylink_get_caps,

	.phylink_mac_link_state	= qca8k_phylink_mac_link_state,

	.phylink_mac_select_pcs	= qca8k_phylink_mac_select_pcs,

	.phylink_mac_config	= qca8k_phylink_mac_config,

	.phylink_mac_link_down	= qca8k_phylink_mac_link_down,

	.phylink_mac_link_up	= qca8k_phylink_mac_link_up,

drivers/net/dsa/qca8k.h

+8 −0
Original line number Diff line number Diff line
@@ -376,6 +376,12 @@ struct qca8k_mdio_cache { 
	u16 hi;

};



struct qca8k_pcs {

	struct phylink_pcs pcs;

	struct qca8k_priv *priv;

	int port;

};



struct qca8k_priv {

	u8 switch_id;

	u8 switch_revision;
@@ -397,6 +403,8 @@ struct qca8k_priv { 
	struct qca8k_mgmt_eth_data mgmt_eth_data;

	struct qca8k_mib_eth_data mib_eth_data;

	struct qca8k_mdio_cache mdio_cache;

	struct qca8k_pcs pcs_port_0;

	struct qca8k_pcs pcs_port_6;

};



struct qca8k_mib_desc {

include/net/dsa.h

+3 −0
Original line number Diff line number Diff line
@@ -788,6 +788,9 @@ struct dsa_switch_ops { 
	void	(*phylink_validate)(struct dsa_switch *ds, int port,

				    unsigned long *supported,

				    struct phylink_link_state *state);

	struct phylink_pcs *(*phylink_mac_select_pcs)(struct dsa_switch *ds,

						      int port,

						      phy_interface_t iface);

	int	(*phylink_mac_link_state)(struct dsa_switch *ds, int port,

					  struct phylink_link_state *state);

	void	(*phylink_mac_config)(struct dsa_switch *ds, int port,

net/dsa/port.c

+15 −0
Original line number Diff line number Diff line
@@ -1053,6 +1053,20 @@ static void dsa_port_phylink_mac_pcs_get_state(struct phylink_config *config, 
	}

}



static struct phylink_pcs *

dsa_port_phylink_mac_select_pcs(struct phylink_config *config,

				phy_interface_t interface)

{

	struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);

	struct dsa_switch *ds = dp->ds;

	struct phylink_pcs *pcs = NULL;



	if (ds->ops->phylink_mac_select_pcs)

		pcs = ds->ops->phylink_mac_select_pcs(ds, dp->index, interface);



	return pcs;

}



static void dsa_port_phylink_mac_config(struct phylink_config *config,

					unsigned int mode,

					const struct phylink_link_state *state)
@@ -1119,6 +1133,7 @@ static void dsa_port_phylink_mac_link_up(struct phylink_config *config, 


static const struct phylink_mac_ops dsa_port_phylink_mac_ops = {

	.validate = dsa_port_phylink_validate,

	.mac_select_pcs = dsa_port_phylink_mac_select_pcs,

	.mac_pcs_get_state = dsa_port_phylink_mac_pcs_get_state,

	.mac_config = dsa_port_phylink_mac_config,

	.mac_an_restart = dsa_port_phylink_mac_an_restart,