Commit a3ace75c authored by yipechai's avatar yipechai Committed by Alex Deucher
Browse files

drm/amdgpu: Optimize amdgpu_umc_ras_late_init/amdgpu_umc_ras_fini function code 



Optimize amdgpu_umc_ras_late_init/amdgpu_umc_ras_fini function code.

Signed-off-by: default avataryipechai <YiPeng.Chai@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 683bac6b

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c

+6 −38
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ int amdgpu_umc_poison_handler(struct amdgpu_device *adev, 
	return ret;

}



static int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,

int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,

		void *ras_error_status,

		struct amdgpu_iv_entry *entry)

{
@@ -139,36 +139,15 @@ static int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 
int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_info)

{

	int r;

	struct ras_fs_if fs_info = {

		.sysfs_name = "umc_err_count",

	};

	struct ras_ih_if ih_info = {

		.cb = amdgpu_umc_process_ras_data_cb,

	};



	if (!adev->umc.ras_if) {

		adev->umc.ras_if =

			kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);

		if (!adev->umc.ras_if)

			return -ENOMEM;

		adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC;

		adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;

		adev->umc.ras_if->sub_block_index = 0;

	}

	ih_info.head = fs_info.head = *adev->umc.ras_if;



	r = amdgpu_ras_late_init(adev, adev->umc.ras_if,

				 &fs_info, &ih_info);

	r = amdgpu_ras_block_late_init(adev, adev->umc.ras_if);

	if (r)

		goto free;

		return r;



	if (amdgpu_ras_is_supported(adev, adev->umc.ras_if->block)) {

		r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);

		if (r)

			goto late_fini;

	} else {

		r = 0;

		goto free;

	}



	/* ras init of specific umc version */
@@ -179,26 +158,15 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_info) 
	return 0;



late_fini:

	amdgpu_ras_late_fini(adev, adev->umc.ras_if, &ih_info);

free:

	kfree(adev->umc.ras_if);

	adev->umc.ras_if = NULL;

	amdgpu_ras_block_late_fini(adev, adev->umc.ras_if);

	return r;

}



void amdgpu_umc_ras_fini(struct amdgpu_device *adev)

{

	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&

			adev->umc.ras_if) {

		struct ras_common_if *ras_if = adev->umc.ras_if;

		struct ras_ih_if ih_info = {

			.head = *ras_if,

			.cb = amdgpu_umc_process_ras_data_cb,

		};



		amdgpu_ras_late_fini(adev, ras_if, &ih_info);

		kfree(ras_if);

	}

			adev->umc.ras_if)

		amdgpu_ras_block_late_fini(adev, adev->umc.ras_if);

}



int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h

+4 −0
Original line number Diff line number Diff line
@@ -85,4 +85,8 @@ void amdgpu_umc_fill_error_record(struct ras_err_data *err_data, 
		uint64_t retired_page,

		uint32_t channel_index,

		uint32_t umc_inst);



int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,

		void *ras_error_status,

		struct amdgpu_iv_entry *entry);

#endif

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

+6 −0
Original line number Diff line number Diff line
@@ -674,6 +674,8 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 


		strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");

		adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;

		adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;

		adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;



		/* If don't define special ras_late_init function, use default ras_late_init */

		if (!adev->umc.ras->ras_block.ras_late_init)
@@ -682,6 +684,10 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 
		/* If don't define special ras_fini function, use default ras_fini */

		if (!adev->umc.ras->ras_block.ras_fini)

				adev->umc.ras->ras_block.ras_fini = amdgpu_umc_ras_fini;



		/* If not defined special ras_cb function, use default ras_cb */

		if (!adev->umc.ras->ras_block.ras_cb)

			adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;

	}

}

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+6 −0
Original line number Diff line number Diff line
@@ -1234,6 +1234,8 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 


		strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");

		adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;

		adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;

		adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;



		/* If don't define special ras_late_init function, use default ras_late_init */

		if (!adev->umc.ras->ras_block.ras_late_init)
@@ -1242,6 +1244,10 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 
		/* If don't define special ras_fini function, use default ras_fini */

		if (!adev->umc.ras->ras_block.ras_fini)

				adev->umc.ras->ras_block.ras_fini = amdgpu_umc_ras_fini;



		/* If not defined special ras_cb function, use default ras_cb */

		if (!adev->umc.ras->ras_block.ras_cb)

			adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;

	}

}