Commit a38b873f authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Fix CW4 programming for dmub30 cached inbox 



[Why]
The conditions for whether we used cached vs non-cached inbox1 depend
on a version check that mismatches what the shared helpers in dmub20
implement.

[How]
Use the dmub_dcn20_use_cached_inbox check for dmub_dcn30 as well.

Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarAnson Jacob <Anson.Jacob@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 163e3bcb

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

+1 −1
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in, 
	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;

}



static inline bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)

bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)

{

	/* Cached inbox is not supported in this fw version range */

	return !(dmub->fw_version >= DMUB_FW_VERSION(1, 0, 0) &&

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

+2 −0
Original line number Diff line number Diff line
@@ -198,4 +198,6 @@ void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) 


union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub);



bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub);



#endif /* _DMUB_DCN20_H_ */

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

+1 −1
Original line number Diff line number Diff line
@@ -155,7 +155,7 @@ void dmub_dcn30_setup_windows(struct dmub_srv *dmub, 
	offset = cw4->offset;



	/* New firmware can support CW4. */

	if (dmub->fw_version > DMUB_FW_VERSION(1, 0, 10)) {

	if (dmub_dcn20_use_cached_inbox(dmub)) {

		REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);

		REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);

		REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);