Unverified Commit a387319e authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!11127 drm/amd/display: Check pipe offset before setting vblank 

Merge Pull Request from: @ci-robot 
 
PR sync from: Jinjiang Tu <tujinjiang@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/IXBHIJ7ZS554CDGR4BBY5UFXYY4WX5R4/ 
 
https://gitee.com/src-openeuler/kernel/issues/IAGSBL 
 
Link:https://gitee.com/openeuler/kernel/pulls/11127

 

Reviewed-by: default avatarYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: default avatarYang Yingliang <yangyingliang@huawei.com>
parents 3e163a9e 75c43df9

drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

+6 −2
Original line number Diff line number Diff line
@@ -211,8 +211,12 @@ bool dce110_vblank_set(struct irq_service *irq_service, 
						   info->ext_id);

	uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;



	struct timing_generator *tg =

			dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;

	struct timing_generator *tg;



	if (pipe_offset >= MAX_PIPES)

		return false;



	tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;



	if (enable) {

		if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {