Commit a379e16a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-qcom', 'clk-mtk', 'clk-versatile' and 'clk-doc' into clk-next 

 - Use ARRAY_SIZE in qcom clk drivers
 - Remove some impractical fallback parent names in qcom clk drivers
 - GCC and RPMcc support for Qualcomm QCM2290 SoCs
 - GCC support for Qualcomm MSM8994/MSM8992 SoCs
 - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
 - Support for Mediatek MT8195 SoCs
 - Make Mediatek clk drivers tristate

* clk-qcom: (44 commits)
  clk: qcom: gdsc: enable optional power domain support
  clk: qcom: videocc-sm8250: use runtime PM for the clock controller
  clk: qcom: dispcc-sm8250: use runtime PM for the clock controller
  dt-bindings: clock: qcom,videocc: add mmcx power domain
  dt-bindings: clock: qcom,dispcc-sm8x50: add mmcx power domain
  clk: qcom: gcc-sc7280: Drop unused array
  clk: qcom: camcc: Add camera clock controller driver for SC7280
  dt-bindings: clock: Add YAML schemas for CAMCC clocks on SC7280
  clk: qcom: Add lpass clock controller driver for SC7280
  dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280
  clk: qcom: Kconfig: Sort the symbol for SC_LPASS_CORECC_7180
  clk: qcom: mmcc-sdm660: Add hw_ctrl flag to venus_core0_gdsc
  clk: qcom: mmcc-sdm660: Add necessary CXCs to venus_gdsc
  clk: qcom: gcc-msm8994: Use ARRAY_SIZE() for num_parents
  clk: qcom: gcc-msm8994: Add proper msm8992 support
  clk: qcom: gcc-msm8994: Add modem reset
  clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIE
  clk: qcom: gcc-msm8994: Add missing clocks
  clk: qcom: gcc-msm8994: Add missing NoC clocks
  clk: qcom: gcc-msm8994: Fix up SPI QUP clocks
  ...

* clk-mtk: (28 commits)
  clk: mediatek: Export clk_ops structures to modules
  clk: mediatek: support COMMON_CLK_MT6779 module build
  clk: mediatek: support COMMON_CLK_MEDIATEK module build
  clk: composite: export clk_register_composite
  clk: mediatek: Add MT8195 apusys clock support
  clk: mediatek: Add MT8195 imp i2c wrapper clock support
  clk: mediatek: Add MT8195 wpesys clock support
  clk: mediatek: Add MT8195 vppsys1 clock support
  clk: mediatek: Add MT8195 vppsys0 clock support
  clk: mediatek: Add MT8195 vencsys clock support
  clk: mediatek: Add MT8195 vdosys1 clock support
  clk: mediatek: Add MT8195 vdosys0 clock support
  clk: mediatek: Add MT8195 vdecsys clock support
  clk: mediatek: Add MT8195 scp adsp clock support
  clk: mediatek: Add MT8195 mfgcfg clock support
  clk: mediatek: Add MT8195 ipesys clock support
  clk: mediatek: Add MT8195 imgsys clock support
  clk: mediatek: Add MT8195 ccusys clock support
  clk: mediatek: Add MT8195 camsys clock support
  clk: mediatek: Add MT8195 infrastructure clock support
  ...

* clk-versatile:
  clk: versatile: hide clock drivers from non-ARM users
  clk: versatile: Rename ICST to CLK_ICST
  clk: versatile: clk-icst: Support 'reg' in addition to 'vco-offset' for register address
  dt-bindings: clock: arm,syscon-icst: Use 'reg' instead of 'vco-offset' for VCO register address

* clk-doc:
  dt-bindings: clk: fixed-mmio-clock: Convert to YAML
parents 1b771839 a8cd038c d4e15d48 7d9e0b12

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: MediaTek Functional Clock Controller for MT8195



maintainers:

  - Chun-Jie Chen <chun-jie.chen@mediatek.com>



description:

  The clock architecture in Mediatek like below

  PLLs -->

          dividers -->

                      muxes

                           -->

                              clock gate



  The devices except apusys_pll provide clock gate control in different IP blocks.

  The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8195-scp_adsp

          - mediatek,mt8195-imp_iic_wrap_s

          - mediatek,mt8195-imp_iic_wrap_w

          - mediatek,mt8195-mfgcfg

          - mediatek,mt8195-vppsys0

          - mediatek,mt8195-wpesys

          - mediatek,mt8195-wpesys_vpp0

          - mediatek,mt8195-wpesys_vpp1

          - mediatek,mt8195-vppsys1

          - mediatek,mt8195-imgsys

          - mediatek,mt8195-imgsys1_dip_top

          - mediatek,mt8195-imgsys1_dip_nr

          - mediatek,mt8195-imgsys1_wpe

          - mediatek,mt8195-ipesys

          - mediatek,mt8195-camsys

          - mediatek,mt8195-camsys_rawa

          - mediatek,mt8195-camsys_yuva

          - mediatek,mt8195-camsys_rawb

          - mediatek,mt8195-camsys_yuvb

          - mediatek,mt8195-camsys_mraw

          - mediatek,mt8195-ccusys

          - mediatek,mt8195-vdecsys_soc

          - mediatek,mt8195-vdecsys

          - mediatek,mt8195-vdecsys_core1

          - mediatek,mt8195-vencsys

          - mediatek,mt8195-vencsys_core1

          - mediatek,mt8195-apusys_pll

  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    scp_adsp: clock-controller@10720000 {

        compatible = "mediatek,mt8195-scp_adsp";

        reg = <0x10720000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_s: clock-controller@11d03000 {

        compatible = "mediatek,mt8195-imp_iic_wrap_s";

        reg = <0x11d03000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_w: clock-controller@11e05000 {

        compatible = "mediatek,mt8195-imp_iic_wrap_w";

        reg = <0x11e05000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    mfgcfg: clock-controller@13fbf000 {

        compatible = "mediatek,mt8195-mfgcfg";

        reg = <0x13fbf000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vppsys0: clock-controller@14000000 {

        compatible = "mediatek,mt8195-vppsys0";

        reg = <0x14000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    wpesys: clock-controller@14e00000 {

        compatible = "mediatek,mt8195-wpesys";

        reg = <0x14e00000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    wpesys_vpp0: clock-controller@14e02000 {

        compatible = "mediatek,mt8195-wpesys_vpp0";

        reg = <0x14e02000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    wpesys_vpp1: clock-controller@14e03000 {

        compatible = "mediatek,mt8195-wpesys_vpp1";

        reg = <0x14e03000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vppsys1: clock-controller@14f00000 {

        compatible = "mediatek,mt8195-vppsys1";

        reg = <0x14f00000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imgsys: clock-controller@15000000 {

        compatible = "mediatek,mt8195-imgsys";

        reg = <0x15000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imgsys1_dip_top: clock-controller@15110000 {

        compatible = "mediatek,mt8195-imgsys1_dip_top";

        reg = <0x15110000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imgsys1_dip_nr: clock-controller@15130000 {

        compatible = "mediatek,mt8195-imgsys1_dip_nr";

        reg = <0x15130000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imgsys1_wpe: clock-controller@15220000 {

        compatible = "mediatek,mt8195-imgsys1_wpe";

        reg = <0x15220000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    ipesys: clock-controller@15330000 {

        compatible = "mediatek,mt8195-ipesys";

        reg = <0x15330000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys: clock-controller@16000000 {

        compatible = "mediatek,mt8195-camsys";

        reg = <0x16000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys_rawa: clock-controller@1604f000 {

        compatible = "mediatek,mt8195-camsys_rawa";

        reg = <0x1604f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys_yuva: clock-controller@1606f000 {

        compatible = "mediatek,mt8195-camsys_yuva";

        reg = <0x1606f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys_rawb: clock-controller@1608f000 {

        compatible = "mediatek,mt8195-camsys_rawb";

        reg = <0x1608f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys_yuvb: clock-controller@160af000 {

        compatible = "mediatek,mt8195-camsys_yuvb";

        reg = <0x160af000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys_mraw: clock-controller@16140000 {

        compatible = "mediatek,mt8195-camsys_mraw";

        reg = <0x16140000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    ccusys: clock-controller@17200000 {

        compatible = "mediatek,mt8195-ccusys";

        reg = <0x17200000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vdecsys_soc: clock-controller@1800f000 {

        compatible = "mediatek,mt8195-vdecsys_soc";

        reg = <0x1800f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vdecsys: clock-controller@1802f000 {

        compatible = "mediatek,mt8195-vdecsys";

        reg = <0x1802f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vdecsys_core1: clock-controller@1803f000 {

        compatible = "mediatek,mt8195-vdecsys_core1";

        reg = <0x1803f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vencsys: clock-controller@1a000000 {

        compatible = "mediatek,mt8195-vencsys";

        reg = <0x1a000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vencsys_core1: clock-controller@1b000000 {

        compatible = "mediatek,mt8195-vencsys_core1";

        reg = <0x1b000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    apusys_pll: clock-controller@190f3000 {

        compatible = "mediatek,mt8195-apusys_pll";

        reg = <0x190f3000 0x1000>;

        #clock-cells = <1>;

    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: MediaTek System Clock Controller for MT8195



maintainers:

  - Chun-Jie Chen <chun-jie.chen@mediatek.com>



description:

  The clock architecture in Mediatek like below

  PLLs -->

          dividers -->

                      muxes

                           -->

                              clock gate



  The apmixedsys provides most of PLLs which generated from SoC 26m.

  The topckgen provides dividers and muxes which provide the clock source to other IP blocks.

  The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8195-topckgen

          - mediatek,mt8195-infracfg_ao

          - mediatek,mt8195-apmixedsys

          - mediatek,mt8195-pericfg_ao

      - const: syscon



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    topckgen: syscon@10000000 {

        compatible = "mediatek,mt8195-topckgen", "syscon";

        reg = <0x10000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    infracfg_ao: syscon@10001000 {

        compatible = "mediatek,mt8195-infracfg_ao", "syscon";

        reg = <0x10001000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    apmixedsys: syscon@1000c000 {

        compatible = "mediatek,mt8195-apmixedsys", "syscon";

        reg = <0x1000c000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    pericfg_ao: syscon@11003000 {

        compatible = "mediatek,mt8195-pericfg_ao", "syscon";

        reg = <0x11003000 0x1000>;

        #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml

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Original line number Diff line number Diff line
@@ -69,6 +69,10 @@ properties: 
      - arm,impd1-vco1

      - arm,impd1-vco2



  reg:

    maxItems: 1

    description: The VCO register



  clocks:

    description: Parent clock for the ICST VCO

    maxItems: 1
@@ -83,6 +87,7 @@ properties: 
  vco-offset:

    $ref: '/schemas/types.yaml#/definitions/uint32'

    description: Offset to the VCO register for the oscillator

    deprecated: true



required:

  - "#clock-cells"

Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt

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Binding for simple memory mapped io fixed-rate clock sources.

The driver reads a clock frequency value from a single 32-bit memory mapped

I/O register and registers it as a fixed rate clock.



It was designed for test systems, like FPGA, not for complete, finished SoCs.



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



Required properties:

- compatible : shall be "fixed-mmio-clock".

- #clock-cells : from common clock binding; shall be set to 0.

- reg : Address and length of the clock value register set.



Optional properties:

- clock-output-names : From common clock binding.



Example:

sysclock: sysclock@fd020004 {

	#clock-cells = <0>;

	compatible = "fixed-mmio-clock";

	reg = <0xfd020004 0x4>;

};

Documentation/devicetree/bindings/clock/fixed-mmio-clock.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Binding for simple memory mapped IO fixed-rate clock sources



description:

  This binding describes a fixed-rate clock for which the frequency can

  be read from a single 32-bit memory mapped I/O register.



  It was designed for test systems, like FPGA, not for complete,

  finished SoCs.



maintainers:

  - Jan Kotas <jank@cadence.com>



properties:

  compatible:

    const: fixed-mmio-clock



  reg:

    maxItems: 1



  "#clock-cells":

    const: 0



  clock-output-names:

    maxItems: 1



required:

  - compatible

  - reg

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    sysclock: sysclock@fd020004 {

      compatible = "fixed-mmio-clock";

      #clock-cells = <0>;

      reg = <0xfd020004 0x4>;

      clock-output-names = "sysclk";

    };

...