Commit a379b01c authored by Vitaly Lifshits's avatar Vitaly Lifshits Committed by Jakub Kicinski
Browse files

e1000e: fix S0ix flow to allow S0i3.2 subset entry



Changed a configuration in the flows to align with
architecture requirements to achieve S0i3.2 substate.

This helps both i219V and i219LM configurations.

Also fixed a typo in the previous commit 632fbd5e
("e1000e: fix S0ix flows for cable connected case").

Fixes: 632fbd5e ("e1000e: fix S0ix flows for cable connected case").
Signed-off-by: default avatarVitaly Lifshits <vitaly.lifshits@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
Reviewed-by: default avatarAlexander Duyck <alexanderduyck@fb.com>
Signed-off-by: default avatarMario Limonciello <mario.limonciello@dell.com>
Link: https://lore.kernel.org/r/20201208185632.151052-1-mario.limonciello@dell.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent c02bd115
Loading
Loading
Loading
Loading
+4 −4
Original line number Diff line number Diff line
@@ -6475,13 +6475,13 @@ static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)

	/* Ungate PGCB clock */
	mac_data = er32(FEXTNVM9);
	mac_data |= BIT(28);
	mac_data &= ~BIT(28);
	ew32(FEXTNVM9, mac_data);

	/* Enable K1 off to enable mPHY Power Gating */
	mac_data = er32(FEXTNVM6);
	mac_data |= BIT(31);
	ew32(FEXTNVM12, mac_data);
	ew32(FEXTNVM6, mac_data);

	/* Enable mPHY power gating for any link and speed */
	mac_data = er32(FEXTNVM8);
@@ -6525,11 +6525,11 @@ static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
	/* Disable K1 off */
	mac_data = er32(FEXTNVM6);
	mac_data &= ~BIT(31);
	ew32(FEXTNVM12, mac_data);
	ew32(FEXTNVM6, mac_data);

	/* Disable Ungate PGCB clock */
	mac_data = er32(FEXTNVM9);
	mac_data &= ~BIT(28);
	mac_data |= BIT(28);
	ew32(FEXTNVM9, mac_data);

	/* Cancel not waking from dynamic