Commit a36f7254 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: Add CRC and DMUB test support 



[Why & How]
- Add CRC for test support
- Add params to allow control into to DMUB.

Reviewed-by: default avatarChris Park <Chris.Park@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a8b53760

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h

+29 −0
Original line number Diff line number Diff line
@@ -161,10 +161,20 @@ struct dcn_optc_registers { 
	uint32_t OTG_CRC_CNTL2;

	uint32_t OTG_CRC0_DATA_RG;

	uint32_t OTG_CRC0_DATA_B;

	uint32_t OTG_CRC1_DATA_B;

	uint32_t OTG_CRC2_DATA_B;

	uint32_t OTG_CRC3_DATA_B;

	uint32_t OTG_CRC1_DATA_RG;

	uint32_t OTG_CRC2_DATA_RG;

	uint32_t OTG_CRC3_DATA_RG;

	uint32_t OTG_CRC0_WINDOWA_X_CONTROL;

	uint32_t OTG_CRC0_WINDOWA_Y_CONTROL;

	uint32_t OTG_CRC0_WINDOWB_X_CONTROL;

	uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;

	uint32_t OTG_CRC1_WINDOWA_X_CONTROL;

	uint32_t OTG_CRC1_WINDOWA_Y_CONTROL;

	uint32_t OTG_CRC1_WINDOWB_X_CONTROL;

	uint32_t OTG_CRC1_WINDOWB_Y_CONTROL;

	uint32_t GSL_SOURCE_SELECT;

	uint32_t DWB_SOURCE_SELECT;

	uint32_t OTG_DSC_START_POSITION;
@@ -464,6 +474,15 @@ struct dcn_optc_registers { 
	type CRC0_R_CR;\

	type CRC0_G_Y;\

	type CRC0_B_CB;\

	type CRC1_R_CR;\

	type CRC1_G_Y;\

	type CRC1_B_CB;\

	type CRC2_R_CR;\

	type CRC2_G_Y;\

	type CRC2_B_CB;\

	type CRC3_R_CR;\

	type CRC3_G_Y;\

	type CRC3_B_CB;\

	type OTG_CRC0_WINDOWA_X_START;\

	type OTG_CRC0_WINDOWA_X_END;\

	type OTG_CRC0_WINDOWA_Y_START;\
@@ -472,6 +491,15 @@ struct dcn_optc_registers { 
	type OTG_CRC0_WINDOWB_X_END;\

	type OTG_CRC0_WINDOWB_Y_START;\

	type OTG_CRC0_WINDOWB_Y_END;\

	type OTG_CRC_WINDOW_DB_EN;\

	type OTG_CRC1_WINDOWA_X_START;\

	type OTG_CRC1_WINDOWA_X_END;\

	type OTG_CRC1_WINDOWA_Y_START;\

	type OTG_CRC1_WINDOWA_Y_END;\

	type OTG_CRC1_WINDOWB_X_START;\

	type OTG_CRC1_WINDOWB_X_END;\

	type OTG_CRC1_WINDOWB_Y_START;\

	type OTG_CRC1_WINDOWB_Y_END;\

	type GSL0_READY_SOURCE_SEL;\

	type GSL1_READY_SOURCE_SEL;\

	type GSL2_READY_SOURCE_SEL;\
@@ -525,6 +553,7 @@ struct dcn_optc_registers { 
#define TG_REG_FIELD_LIST_DCN3_2(type) \

	type OTG_H_TIMING_DIV_MODE_MANUAL;





struct dcn_optc_shift {

	TG_REG_FIELD_LIST(uint8_t)

	TG_REG_FIELD_LIST_DCN3_2(uint8_t)

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

+2 −0
Original line number Diff line number Diff line
@@ -261,6 +261,8 @@ struct dmub_srv_hw_params { 
	bool usb4_cm_version;

	bool fw_in_system_memory;

	bool dpia_hpd_int_enable_supported;

	bool disable_clock_gate;

	bool disallow_dispclk_dppclk_ds;

};



/**

drivers/gpu/drm/amd/display/include/dal_asic_id.h

+1 −0
Original line number Diff line number Diff line
@@ -246,6 +246,7 @@ enum { 


#define AMDGPU_FAMILY_GC_11_0_0 145

#define AMDGPU_FAMILY_GC_11_0_1 148

#define AMDGPU_FAMILY_GC_11_5_0 150

#define GC_11_0_0_A0 0x1

#define GC_11_0_2_A0 0x10

#define GC_11_0_3_A0 0x20