Unverified Commit a35707c3 authored by Heiko Stuebner's avatar Heiko Stuebner Committed by Palmer Dabbelt
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riscv: add memory-type errata for T-Head 



Some current cpus based on T-Head cores implement memory-types
way different than described in the svpbmt spec even going
so far as using PTE bits marked as reserved.

Add the T-Head vendor-id and necessary errata code to
replace the affected instructions.

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Tested-by: default avatarSamuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220511192921.2223629-13-heiko@sntech.de


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 1745cfaf

arch/riscv/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -333,6 +333,12 @@ config RISCV_ALTERNATIVE 
	  code patching is performed once in the boot stages. It means

	  that the overhead from this mechanism is just taken once.



config RISCV_ALTERNATIVE_EARLY

	bool

	depends on RISCV_ALTERNATIVE

	help

	  Allows early patching of the kernel for special errata



config RISCV_ISA_C

	bool "Emit compressed instructions when building Linux"

	default y

arch/riscv/Kconfig.erratas

+21 −0
Original line number Diff line number Diff line
@@ -33,4 +33,25 @@ config ERRATA_SIFIVE_CIP_1200 


	  If you don't know what to do here, say "Y".



config ERRATA_THEAD

	bool "T-HEAD errata"

	select RISCV_ALTERNATIVE

	help

	  All T-HEAD errata Kconfig depend on this Kconfig. Disabling

	  this Kconfig will disable all T-HEAD errata. Please say "Y"

	  here if your platform uses T-HEAD CPU cores.



	  Otherwise, please say "N" here to avoid unnecessary overhead.



config ERRATA_THEAD_PBMT

	bool "Apply T-Head memory type errata"

	depends on ERRATA_THEAD && 64BIT

	select RISCV_ALTERNATIVE_EARLY

	default y

	help

	  This will apply the memory type errata to handle the non-standard

	  memory type bits in page-table-entries on T-Head SoCs.



	  If you don't know what to do here, say "Y".



endmenu

arch/riscv/errata/Makefile

+1 −0
Original line number Diff line number Diff line 
obj-$(CONFIG_ERRATA_SIFIVE) += sifive/

obj-$(CONFIG_ERRATA_THEAD) += thead/

arch/riscv/errata/sifive/errata.c

+6 −1
Original line number Diff line number Diff line
@@ -88,10 +88,15 @@ void __init_or_module sifive_errata_patch_func(struct alt_entry *begin, 
					       unsigned int stage)

{

	struct alt_entry *alt;

	u32 cpu_req_errata = sifive_errata_probe(archid, impid);

	u32 cpu_req_errata;

	u32 cpu_apply_errata = 0;

	u32 tmp;



	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)

		return;



	cpu_req_errata = sifive_errata_probe(archid, impid);



	for (alt = begin; alt < end; alt++) {

		if (alt->vendor_id != SIFIVE_VENDOR_ID)

			continue;

arch/riscv/errata/thead/Makefile

0 → 100644
+11 −0
Original line number Diff line number Diff line 
ifdef CONFIG_RISCV_ALTERNATIVE_EARLY

CFLAGS_errata.o := -mcmodel=medany

ifdef CONFIG_FTRACE

CFLAGS_REMOVE_errata.o = $(CC_FLAGS_FTRACE)

endif

ifdef CONFIG_KASAN

KASAN_SANITIZE_errata.o := n

endif

endif



obj-y += errata.o