Commit a346129e authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab Committed by Greg Kroah-Hartman
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staging: hikey9xx: phy-hi3670-usb3: use bitfield macros 



Cleanup the bitfield macros by using FIELD_PREP() and GENMASK().

While here, place all hexadecimal values in lowercase.

Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/ac56b97a99ec278d2f40e07e7e07adef36d45d09.1611052729.git.mchehab+huawei@kernel.org


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b4783da2

drivers/staging/hikey9xx/phy-hi3670-usb3.c

+28 −33
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
 * Authors: Yu Chen <chenyu56@huawei.com>

 */



#include <linux/bitfield.h>

#include <linux/clk.h>

#include <linux/kernel.h>

#include <linux/mfd/syscon.h>
@@ -41,15 +42,15 @@ 
#define SC_CLK_USB3PHY_3MUX1_SEL	BIT(25)



#define USB3OTG_CTRL0			(0x00)

#define USB3OTG_CTRL3			(0x0C)

#define USB3OTG_CTRL3			(0x0c)

#define USB3OTG_CTRL4			(0x10)

#define USB3OTG_CTRL5			(0x14)

#define USB3OTG_CTRL7			(0x1C)

#define USB3OTG_CTRL7			(0x1c)

#define USB_MISC_CFG50			(0x50)

#define USB_MISC_CFG54			(0x54)

#define USB_MISC_CFG58			(0x58)

#define USB_MISC_CFG5C			(0x5C)

#define USB_MISC_CFGA0			(0xA0)

#define USB_MISC_CFG5C			(0x5c)

#define USB_MISC_CFGA0			(0xa0)

#define TCA_CLK_RST			(0x200)

#define TCA_INTR_EN			(0x204)

#define TCA_INTR_STS			(0x208)
@@ -66,14 +67,14 @@ 


#define CTRL5_USB2_SIDDQ		BIT(0)



#define CTRL7_USB2_REFCLKSEL_MASK	(3 << 3)

#define CTRL7_USB2_REFCLKSEL_ABB	(3 << 3)

#define CTRL7_USB2_REFCLKSEL_PAD	(2 << 3)

#define CTRL7_USB2_REFCLKSEL_MASK	GENMASK(4, 3)

#define CTRL7_USB2_REFCLKSEL_ABB	(BIT(4) | BIT(3))

#define CTRL7_USB2_REFCLKSEL_PAD	BIT(4)



#define CFG50_USB3_PHY_TEST_POWERDOWN	BIT(23)



#define CFG54_USB31PHY_CR_ADDR_MASK	(0xFFFF)

#define CFG54_USB31PHY_CR_ADDR_SHIFT	(16)

#define CFG54_USB31PHY_CR_ADDR_MASK	GENMASK(31, 16)



#define CFG54_USB3PHY_REF_USE_PAD	BIT(12)

#define CFG54_PHY0_PMA_PWR_STABLE	BIT(11)

#define CFG54_PHY0_PCS_PWR_STABLE	BIT(9)
@@ -84,8 +85,7 @@ 
#define CFG54_USB31PHY_CR_CLK		BIT(2)

#define CFG54_USB3_PHY0_ANA_PWR_EN	BIT(1)



#define CFG58_USB31PHY_CR_DATA_MASK     (0xFFFF)

#define CFG58_USB31PHY_CR_DATA_RD_START (16)

#define CFG58_USB31PHY_CR_DATA_MASK     GENMASK(31, 16)



#define CFG5C_USB3_PHY0_SS_MPLLA_SSC_EN	BIT(1)
@@ -102,20 +102,20 @@ 
#define CLK_RST_SUSPEND_CLK_EN		BIT(0)



#define GCFG_ROLE_HSTDEV		BIT(4)

#define GCFG_OP_MODE			(3 << 0)

#define GCFG_OP_MODE			GENMASK(1, 0)

#define GCFG_OP_MODE_CTRL_SYNC_MODE	BIT(0)



#define TCPC_VALID			BIT(4)

#define TCPC_LOW_POWER_EN		BIT(3)

#define TCPC_MUX_CONTROL_MASK		(3 << 0)

#define TCPC_MUX_CONTROL_MASK		GENMASK(1, 0)

#define TCPC_MUX_CONTROL_USB31		BIT(0)



#define SYSMODE_CFG_TYPEC_DISABLE	BIT(3)



#define VBUS_CTRL_POWERPRESENT_OVERRD	(3 << 2)

#define VBUS_CTRL_VBUSVALID_OVERRD	(3 << 0)

#define VBUS_CTRL_POWERPRESENT_OVERRD	GENMASK(3, 2)

#define VBUS_CTRL_VBUSVALID_OVERRD	GENMASK(1, 0)



#define KIRIN970_USB_DEFAULT_PHY_PARAM	(0xFDFEE4)

#define KIRIN970_USB_DEFAULT_PHY_PARAM	(0xfdfee4)

#define KIRIN970_USB_DEFAULT_PHY_VBOOST	(0x5)



#define TX_VBOOST_LVL_REG		(0xf)
@@ -162,16 +162,14 @@ static int hi3670_phy_cr_set_sel(struct regmap *usb31misc) 


static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction)

{

	int ret;

	int ret, reg;



	if (direction)

		ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,

					 CFG54_USB31PHY_CR_WR_EN,

					 CFG54_USB31PHY_CR_WR_EN);

		reg = CFG54_USB31PHY_CR_WR_EN;

	else

		ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,

					 CFG54_USB31PHY_CR_RD_EN,

					 CFG54_USB31PHY_CR_RD_EN);

		reg = CFG54_USB31PHY_CR_RD_EN;



	ret = regmap_update_bits(usb31misc, USB_MISC_CFG54, reg, reg);



	if (ret)

		return ret;
@@ -180,10 +178,8 @@ static int hi3670_phy_cr_start(struct regmap *usb31misc, int direction) 
	if (ret)

		return ret;



	ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,

	return regmap_update_bits(usb31misc, USB_MISC_CFG54,

				  CFG54_USB31PHY_CR_RD_EN | CFG54_USB31PHY_CR_WR_EN, 0);



	return ret;

}



static int hi3670_phy_cr_wait_ack(struct regmap *usb31misc)
@@ -216,9 +212,9 @@ static int hi3670_phy_cr_set_addr(struct regmap *usb31misc, u32 addr) 
	if (ret)

		return ret;



	reg &= ~(CFG54_USB31PHY_CR_ADDR_MASK << CFG54_USB31PHY_CR_ADDR_SHIFT);

	reg |= ((addr & CFG54_USB31PHY_CR_ADDR_MASK) << CFG54_USB31PHY_CR_ADDR_SHIFT);

	ret = regmap_write(usb31misc, USB_MISC_CFG54, reg);

	reg = FIELD_PREP(CFG54_USB31PHY_CR_ADDR_MASK, addr);

	ret = regmap_update_bits(usb31misc, USB_MISC_CFG54,

				 CFG54_USB31PHY_CR_ADDR_MASK, reg);



	return ret;

}
@@ -255,8 +251,7 @@ static int hi3670_phy_cr_read(struct regmap *usb31misc, u32 addr, u32 *val) 
	if (ret)

		return ret;



	*val = (reg >> CFG58_USB31PHY_CR_DATA_RD_START) &

		CFG58_USB31PHY_CR_DATA_MASK;

	*val = FIELD_GET(CFG58_USB31PHY_CR_DATA_MASK, reg);



	return 0;

}
@@ -281,7 +276,7 @@ static int hi3670_phy_cr_write(struct regmap *usb31misc, u32 addr, u32 val) 
		return ret;



	ret = regmap_write(usb31misc, USB_MISC_CFG58,

			   val & CFG58_USB31PHY_CR_DATA_MASK);

			   FIELD_PREP(CFG58_USB31PHY_CR_DATA_MASK, val));

	if (ret)

		return ret;