Commit a338847a authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Call {vlv,chv}_prepare_pll() from {vlv,chv}_enable_pll() 



We always call the vlv/chv prepare_pll() just before enable_pll().
Move the calls into the enable_pll() funcs. We can also
consolidate the DPLL_VCO_ENABLE checks while at it.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-10-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 98b27e79

drivers/gpu/drm/i915/display/intel_display.c

+2 −5
Original line number Diff line number Diff line
@@ -3576,13 +3576,10 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, 


	intel_encoders_pre_pll_enable(state, crtc);



	if (IS_CHERRYVIEW(dev_priv)) {

		chv_prepare_pll(new_crtc_state);

	if (IS_CHERRYVIEW(dev_priv))

		chv_enable_pll(new_crtc_state);

	} else {

		vlv_prepare_pll(new_crtc_state);

	else

		vlv_enable_pll(new_crtc_state);

	}



	intel_encoders_pre_enable(state, crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

+119 −126
Original line number Diff line number Diff line
@@ -1467,112 +1467,7 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, 
	vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);

}



static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;



	intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);

	intel_de_posting_read(dev_priv, DPLL(pipe));

	udelay(150);



	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))

		drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);

}



void vlv_enable_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;



	assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);



	/* PLL is protected by panel, make sure we can write it */

	assert_panel_unlocked(dev_priv, pipe);



	if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE)

		_vlv_enable_pll(crtc_state);



	intel_de_write(dev_priv, DPLL_MD(pipe),

		       crtc_state->dpll_hw_state.dpll_md);

	intel_de_posting_read(dev_priv, DPLL_MD(pipe));

}





static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	enum dpio_channel port = vlv_pipe_to_channel(pipe);

	u32 tmp;



	vlv_dpio_get(dev_priv);



	/* Enable back the 10bit clock to display controller */

	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));

	tmp |= DPIO_DCLKP_EN;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);



	vlv_dpio_put(dev_priv);



	/*

	 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.

	 */

	udelay(1);



	/* Enable PLL */

	intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);



	/* Check PLL is locked */

	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))

		drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);

}



void chv_enable_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;



	assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);



	/* PLL is protected by panel, make sure we can write it */

	assert_panel_unlocked(dev_priv, pipe);



	if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE)

		_chv_enable_pll(crtc_state);



	if (pipe != PIPE_A) {

		/*

		 * WaPixelRepeatModeFixForC0:chv

		 *

		 * DPLLCMD is AWOL. Use chicken bits to propagate

		 * the value from DPLLBMD to either pipe B or C.

		 */

		intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));

		intel_de_write(dev_priv, DPLL_MD(PIPE_B),

			       crtc_state->dpll_hw_state.dpll_md);

		intel_de_write(dev_priv, CBR4_VLV, 0);

		dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;



		/*

		 * DPLLB VGA mode also seems to cause problems.

		 * We should always have it disabled.

		 */

		drm_WARN_ON(&dev_priv->drm,

			    (intel_de_read(dev_priv, DPLL(PIPE_B)) &

			     DPLL_VGA_MODE_DIS) == 0);

	} else {

		intel_de_write(dev_priv, DPLL_MD(pipe),

			       crtc_state->dpll_hw_state.dpll_md);

		intel_de_posting_read(dev_priv, DPLL_MD(pipe));

	}

}



void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)

static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1581,15 +1476,6 @@ void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) 
	u32 bestn, bestm1, bestm2, bestp1, bestp2;

	u32 coreclk, reg_val;



	/* Enable Refclk */

	intel_de_write(dev_priv, DPLL(pipe),

		       crtc_state->dpll_hw_state.dpll &

		       ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));



	/* No need to actually set up the DPLL with DSI */

	if ((crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)

		return;



	vlv_dpio_get(dev_priv);



	bestn = crtc_state->dpll.n;
@@ -1671,7 +1557,47 @@ void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) 
	vlv_dpio_put(dev_priv);

}



void chv_prepare_pll(const struct intel_crtc_state *crtc_state)

static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;



	intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);

	intel_de_posting_read(dev_priv, DPLL(pipe));

	udelay(150);



	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))

		drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);

}



void vlv_enable_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;



	assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);



	/* PLL is protected by panel, make sure we can write it */

	assert_panel_unlocked(dev_priv, pipe);



	/* Enable Refclk */

	intel_de_write(dev_priv, DPLL(pipe),

		       crtc_state->dpll_hw_state.dpll &

		       ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));



	if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) {

		vlv_prepare_pll(crtc_state);

		_vlv_enable_pll(crtc_state);

	}



	intel_de_write(dev_priv, DPLL_MD(pipe),

		       crtc_state->dpll_hw_state.dpll_md);

	intel_de_posting_read(dev_priv, DPLL_MD(pipe));

}



static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1682,14 +1608,6 @@ void chv_prepare_pll(const struct intel_crtc_state *crtc_state) 
	u32 dpio_val;

	int vco;



	/* Enable Refclk and SSC */

	intel_de_write(dev_priv, DPLL(pipe),

		       crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);



	/* No need to actually set up the DPLL with DSI */

	if ((crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)

		return;



	bestn = crtc_state->dpll.n;

	bestm2_frac = crtc_state->dpll.m2 & 0x3fffff;

	bestm1 = crtc_state->dpll.m1;
@@ -1775,6 +1693,83 @@ void chv_prepare_pll(const struct intel_crtc_state *crtc_state) 
	vlv_dpio_put(dev_priv);

}



static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	enum dpio_channel port = vlv_pipe_to_channel(pipe);

	u32 tmp;



	vlv_dpio_get(dev_priv);



	/* Enable back the 10bit clock to display controller */

	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));

	tmp |= DPIO_DCLKP_EN;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);



	vlv_dpio_put(dev_priv);



	/*

	 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.

	 */

	udelay(1);



	/* Enable PLL */

	intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);



	/* Check PLL is locked */

	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))

		drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);

}



void chv_enable_pll(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;



	assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);



	/* PLL is protected by panel, make sure we can write it */

	assert_panel_unlocked(dev_priv, pipe);



	/* Enable Refclk and SSC */

	intel_de_write(dev_priv, DPLL(pipe),

		       crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);



	if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) {

		chv_prepare_pll(crtc_state);

		_chv_enable_pll(crtc_state);

	}



	if (pipe != PIPE_A) {

		/*

		 * WaPixelRepeatModeFixForC0:chv

		 *

		 * DPLLCMD is AWOL. Use chicken bits to propagate

		 * the value from DPLLBMD to either pipe B or C.

		 */

		intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));

		intel_de_write(dev_priv, DPLL_MD(PIPE_B),

			       crtc_state->dpll_hw_state.dpll_md);

		intel_de_write(dev_priv, CBR4_VLV, 0);

		dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;



		/*

		 * DPLLB VGA mode also seems to cause problems.

		 * We should always have it disabled.

		 */

		drm_WARN_ON(&dev_priv->drm,

			    (intel_de_read(dev_priv, DPLL(PIPE_B)) &

			     DPLL_VGA_MODE_DIS) == 0);

	} else {

		intel_de_write(dev_priv, DPLL_MD(pipe),

			       crtc_state->dpll_hw_state.dpll_md);

		intel_de_posting_read(dev_priv, DPLL_MD(pipe));

	}

}



/**

 * vlv_force_pll_on - forcibly enable just the PLL

 * @dev_priv: i915 private structure
@@ -1802,11 +1797,9 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 


	if (IS_CHERRYVIEW(dev_priv)) {

		chv_compute_dpll(crtc_state);

		chv_prepare_pll(crtc_state);

		chv_enable_pll(crtc_state);

	} else {

		vlv_compute_dpll(crtc_state);

		vlv_prepare_pll(crtc_state);

		vlv_enable_pll(crtc_state);

	}

drivers/gpu/drm/i915/display/intel_dpll.h

+4 −5
Original line number Diff line number Diff line
@@ -25,14 +25,13 @@ void chv_compute_dpll(struct intel_crtc_state *crtc_state); 
int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,

		     const struct dpll *dpll);

void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);

void i9xx_enable_pll(const struct intel_crtc_state *crtc_state);

void vlv_enable_pll(const struct intel_crtc_state *crtc_state);



void chv_enable_pll(const struct intel_crtc_state *crtc_state);

void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe);

void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe);

void vlv_enable_pll(const struct intel_crtc_state *crtc_state);

void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe);

void i9xx_enable_pll(const struct intel_crtc_state *crtc_state);

void i9xx_disable_pll(const struct intel_crtc_state *crtc_state);

void vlv_prepare_pll(const struct intel_crtc_state *crtc_state);

void chv_prepare_pll(const struct intel_crtc_state *crtc_state);

bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,

			struct dpll *best_clock);

int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);