Commit a331f5fd authored by Tony Luck's avatar Tony Luck Committed by Ingo Molnar
Browse files

x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN 



New CPU model, same MSRs to control and read the inventory number.

Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@intel.com
parent 301cddc2

arch/x86/kernel/cpu/mce/intel.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) 
	case INTEL_FAM6_BROADWELL_X:

	case INTEL_FAM6_BROADWELL_X:

	case INTEL_FAM6_SKYLAKE_X:

	case INTEL_FAM6_SKYLAKE_X:

	case INTEL_FAM6_ICELAKE_X:

	case INTEL_FAM6_ICELAKE_X:

	case INTEL_FAM6_SAPPHIRERAPIDS_X:

	case INTEL_FAM6_XEON_PHI_KNL:

	case INTEL_FAM6_XEON_PHI_KNL:

	case INTEL_FAM6_XEON_PHI_KNM:

	case INTEL_FAM6_XEON_PHI_KNM: