Commit a33095f4 authored by Like Xu's avatar Like Xu Committed by Paolo Bonzini
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KVM: x86/pmu: Update comments for AMD gp counters 



The obsolete comment could more accurately state that AMD platforms
have two base MSR addresses and two different maximum numbers
for gp counters, depending on the X86_FEATURE_PERFCTR_CORE feature.

Signed-off-by: default avatarLike Xu <likexu@tencent.com>
Message-Id: <20220518132512.37864-2-likexu@tencent.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent d1c88a40

arch/x86/kvm/pmu.c

+5 −2
Original line number Diff line number Diff line
@@ -44,7 +44,9 @@ static const struct x86_cpu_id vmx_icl_pebs_cpu[] = { 
 *   However AMD doesn't support fixed-counters;

 * - There are three types of index to access perf counters (PMC):

 *     1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD

 *        has MSR_K7_PERFCTRn.

 *        has MSR_K7_PERFCTRn and, for families 15H and later,

 *        MSR_F15H_PERF_CTRn, where MSR_F15H_PERF_CTR[0-3] are

 *        aliased to MSR_K7_PERFCTRn.

 *     2. MSR Index (named idx): This normally is used by RDPMC instruction.

 *        For instance AMD RDPMC instruction uses 0000_0003h in ECX to access

 *        C001_0007h (MSR_K7_PERCTR3). Intel has a similar mechanism, except
@@ -56,7 +58,8 @@ static const struct x86_cpu_id vmx_icl_pebs_cpu[] = { 
 *        between pmc and perf counters is as the following:

 *        * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters

 *                 [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed

 *        * AMD:   [0 .. AMD64_NUM_COUNTERS-1] <=> gp counters

 *        * AMD:   [0 .. AMD64_NUM_COUNTERS-1] and, for families 15H

 *          and later, [0 .. AMD64_NUM_COUNTERS_CORE-1] <=> gp counters

 */



static struct kvm_pmu_ops kvm_pmu_ops __read_mostly;