Commit a328ca7e authored by Neil Armstrong's avatar Neil Armstrong
Browse files

drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate 



The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency
higher than 10MHz for the TX Escape Clock, thus make the target rate
configurable.

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: default avatarPhilippe Cornu <philippe.cornu@st.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200904125531.15248-1-narmstrong@baylibre.com
parent 33f29081

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c

+20 −5
Original line number Diff line number Diff line
@@ -605,15 +605,30 @@ static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 


static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)

{

	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;

	unsigned int esc_rate; /* in MHz */

	u32 esc_clk_division;

	int ret;



	/*

	 * The maximum permitted escape clock is 20MHz and it is derived from

	 * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:

	 *

	 *     (lane_mbps >> 3) / esc_clk_division < 20

	 * lanebyteclk, which is running at "lane_mbps / 8".

	 */

	if (phy_ops->get_esc_clk_rate) {

		ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data,

						&esc_rate);

		if (ret)

			DRM_DEBUG_DRIVER("Phy get_esc_clk_rate() failed\n");

	} else

		esc_rate = 20; /* Default to 20MHz */



	/*

	 * We want :

	 *     (lane_mbps >> 3) / esc_clk_division < X

	 * which is:

	 *     (lane_mbps >> 3) / 20 > esc_clk_division

	 *     (lane_mbps >> 3) / X > esc_clk_division

	 */

	u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;

	esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;



	dsi_write(dsi, DSI_PWR_UP, RESET);

include/drm/bridge/dw_mipi_dsi.h

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ struct dw_mipi_dsi_phy_ops { 
			     unsigned int *lane_mbps);

	int (*get_timing)(void *priv_data, unsigned int lane_mbps,

			  struct dw_mipi_dsi_dphy_timing *timing);

	int (*get_esc_clk_rate)(void *priv_data, unsigned int *esc_clk_rate);

};



struct dw_mipi_dsi_host_ops {